Datasheet

Table 37-31. Offset and Gain correction feature
Gain
Factor
Conditions Offset
Error (mV)
Gain Error
(mV)
Total Unadjusted
Error (LSB)
0.5x In differential mode, 1x gain, V
DDANA
=3.0V,
V
REF
=1.0V, 350kSps at 25°C
0.25 1.0 2.4
1x 0.20 0.10 1.5
2x 0.15 -0.15 2.7
8x -0.05 0.05 3.2
16x 0.10 -0.05 6.1
37.11.4.3 Inputs and Sample and Hold Acquisition Times
The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in
order to achieve maximum accuracy. Seen externally, the ADC input consists of a resistor (
SAMPLE
) and
a capacitor (
SAMPLE
). In addition, the source resistance (
SOURCE
) must be taken into account when
calculating the required sample and hold time. The next figure shows the ADC input channel equivalent
circuit.
Figure 37-5. ADC Input
R
SOURCE
R
SAMPLE
Analog Input
AINx
C
SAMPLE
V
IN
VDDANA/2
To achieve n bits of accuracy, the 
SAMPLE
capacitor must be charged at least to a voltage of

CSAMPLE
 
IN
× 1 +  2
  + 1
The minimum sampling time 
SAMPLEHOLD
for a given 
SOURCE
can be found using this formula:

SAMPLEHOLD
 
SAMPLE
+ 
SOURCE
× 
SAMPLE
×  + 1 × ln 2
for a 12 bits accuracy:

SAMPLEHOLD
 
SAMPLE
+ 
SOURCE
× 
SAMPLE
× 9.02
where

SAMPLEHOLD
=
1
2 × 
ADC
SAM D21 Family
Electrical Characteristics
© 2018 Microchip Technology Inc.
Datasheet Complete
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