Datasheet

– VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
– VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
3. The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply.
The ADC performance of these pins will not be the same as all the other ADC channels on pins
powered from the VDDANA power supply.
4. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error
in V x 100) / (Vref/GAIN)
37.11.4.1 Performance with the Averaging Digital Feature
Averaging is a feature which increases the sample accuracy. ADC automatically computes an average
value of multiple consecutive conversions. The numbers of samples to be averaged is specified by the
Number-of-Samples-to-be-collected bit group in the Average Control register
(AVGCTRL.SAMPLENUM[3:0]) and the averaged output is available in the Result register (RESULT).
Table 37-29. Averaging Feature (Device Variant A)
Average
Number
Conditions SNR
(dB)
SINAD
(dB)
SFDR
(dB)
ENOB
(bits)
1 In differential mode, 1x gain,
V
DDANA
=3.0V, V
REF
=1.0V, 350kSps at
25°C
66.0 65.0 72.8 9.75
8 67.6 65.8 75.1 10.62
32 69.7 67.1 75.3 10.85
128 70.4 67.5 75.5 10.91
Table 37-30. Averaging Feature (Device Variant B,C, D and L)
Average
Number
Conditions SNR
(dB)
SINAD
(dB)
SFDR
(dB)
ENOB
(bits)
1 In differential mode, 1x gain,
V
DDANA
=3.0V, V
REF
=1.0V, 350kSps at
25°C
66.0 65.0 72.8 10.5
8 67.6 65.8 75.1 10.62
32 69.7 67.1 75.3 10.85
128 70.4 67.5 75.5 10.91
37.11.4.2 Performance with the hardware offset and gain correction
Inherent gain and offset errors affect the absolute accuracy of the ADC. The offset error cancellation is
handled by the Offset Correction register (OFFSETCORR) and the gain error cancellation, by the Gain
Correction register (GAINCORR). The offset and gain correction value is subtracted from the converted
data before writing the Result register (RESULT).
SAM D21 Family
Electrical Characteristics
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 1005