Datasheet

ManualsBrandsMicrochip ManualsARM MicrocontrollersARM® Cortex® M0+ SAM Microcontroller 32bit 256KB TQFP

SAM D21 Family

Low-Power, 32-bit Cortex-M0+ MCU with Advanced Analog

and PWM

Features

• Processor

– ARM

Cortex

-M0+ CPU running at up to 48 MHz

• Single-cycle hardware multiplier

• Micro Trace Buffer (MTB)

• Memories

– 32/64/128/256 KB in-system self-programmable Flash

– 4/8/16/32 KB SRAM Memory

• System

– Power-on Reset (POR) and Brown-out Detection (BOD)

– Internal and external clock options with 48 MHz Digital Frequency-Locked Loop (DFLL48M)

and 48 MHz to 96 MHz Fractional Digital Phase-Locked Loop (FDPLL96M)

– External Interrupt Controller (EIC)

– 16 external interrupts

– One Non-maskable Interrupt (NMI)

– Two-pin Serial Wire Debug (SWD) programming, test and debugging interface

• Low Power

– Idle and Stand-by Sleep modes

– SleepWalking peripherals

• Peripherals

– 12-channel Direct Memory Access Controller (DMAC)

– 12-channel Event System

– Up to five 16-bit Timer/Counters (TC), configurable as either:

• One 16-bit TC with two compare/capture channels

• One 8-bit TC with two compare/capture channels

• One 32-bit TC with two compare/capture channels, by using two TCs

– Up to four 24-bit Timer/Counters for Control (TCC), with extended functions:

• Up to four compare channels with optional complementary output

• Generation of synchronized pulse width modulation (PWM) pattern across port pins

• Deterministic fault protection, fast decay and configurable dead-time between

complementary output

• Dithering that increase resolution with up to 5 bit and reduce quantization error

– 32-bit Real Time Counter (RTC) with clock/calendar function

– Watchdog Timer (WDT)

Datasheet Complete

DS40001882D-page 1

Summary of content (1202 pages)

PAGE 1
SAM D21 Family Low-Power, 32-bit Cortex-M0+ MCU with Advanced Analog and PWM Features • • • • • Processor – ARM® Cortex®-M0+ CPU running at up to 48 MHz • Single-cycle hardware multiplier • Micro Trace Buffer (MTB) Memories – 32/64/128/256 KB in-system self-programmable Flash – 4/8/16/32 KB SRAM Memory System – Power-on Reset (POR) and Brown-out Detection (BOD) – Internal and external clock options with 48 MHz Digital Frequency-Locked Loop (DFLL48M) and 48 MHz to 96 MHz Fractional Digital Phase-Locked
PAGE 2
SAM D21 Family – – – – – – – – • • • • • CRC-32 generator One full-speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface • Embedded host and device function • Eight endpoints Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as either: • USART with full-duplex and single-wire half-duplex configuration • I2C up to 3.
PAGE 3
Table of Contents Features.......................................................................................................................... 1 1. Description...............................................................................................................12 2. Configuration Summary...........................................................................................13 3. Ordering Information(1).........................................................................................
PAGE 4
SAM D21 Family 13. DSU - Device Service Unit...................................................................................... 71 13.1. Overview.................................................................................................................................... 71 13.2. Features..................................................................................................................................... 71 13.3. Block Diagram..........................................................
PAGE 5
SAM D21 Family 17.2. 17.3. 17.4. 17.5. 17.6. 17.7. 17.8. Features................................................................................................................................... 172 Block Diagram.......................................................................................................................... 174 Signal Description.................................................................................................................... 174 Product Dependencies...........
PAGE 6
SAM D21 Family 21.8. Register Description................................................................................................................. 372 22. NVMCTRL – Nonvolatile Memory Controller.........................................................383 22.1. 22.2. 22.3. 22.4. 22.5. 22.6. 22.7. 22.8. Overview.................................................................................................................................. 383 Features................................................
PAGE 7
SAM D21 Family 26.8. Register Description................................................................................................................. 486 27. SERCOM SPI – SERCOM Serial Peripheral Interface..........................................510 27.1. 27.2. 27.3. 27.4. 27.5. 27.6. 27.7. 27.8. Overview.................................................................................................................................. 510 Features.......................................................
PAGE 8
SAM D21 Family 31.3. 31.4. 31.5. 31.6. 31.7. 31.8. Block Diagram.......................................................................................................................... 705 Signal Description.................................................................................................................... 706 Product Dependencies............................................................................................................. 706 Functional Description.........................
PAGE 9
SAM D21 Family 36.1. 36.2. 36.3. 36.4. 36.5. 36.6. Overview.................................................................................................................................. 977 Features................................................................................................................................... 977 Block Diagram.......................................................................................................................... 978 Signal Description...............
PAGE 10
SAM D21 Family 40.1. Disclaimer...............................................................................................................................1099 40.2. Thermal Considerations......................................................................................................... 1099 40.3. Absolute Maximum Ratings....................................................................................................1099 40.4. General Operating Ratings............................................
PAGE 11
SAM D21 Family 45.12. 45.13. 45.14. 45.15. 45.16. 45.17. 45.18. 45.19. Rev. H – 01/2016....................................................................................................................1186 Rev. G – 09/2015................................................................................................................... 1187 Rev. F – 07/2015.................................................................................................................... 1187 Rev. E – 02/2015............
PAGE 12
SAM D21 Family Description 1. Description ® ® The SAM D21 is a series of low-power microcontrollers using the 32-bit ARM Cortex -M0+ processor, and ranging from 32-pins to 64-pins with up to 256 KB Flash and 32 KB of SRAM. The SAM D21 operate at a maximum frequency of 48 MHz and reach 2.46 CoreMark/MHz.
PAGE 13
SAM D21 Family Configuration Summary Configuration Summary Table 2-1.
PAGE 14
SAM D21 Family Configuration Summary ...........
PAGE 15
SAM D21 Family Ordering Information(1) 3.
PAGE 16
SAM D21 Family Block Diagram Block Diagram SERIAL WIRE SWDIO DEVICE SERVICE UNIT M 256/128/64/32KB NVM 32/16/8/4KB RAM NVM CONTROLLER Cache SRAM CONTROLLER M S S M HIGH-SPEED BUS MATRIX PERIPHERAL ACCESS CONTROLLER S AHB-APB BRIDGE B S USB FS DEVICE MINI-HOST S AHB-APB BRIDGE A DMA 66xxSERCOM SERCOM VREF OSC32K XOSC32K DMA OSC8M 5 x TIMER / COUNTER 8 x Timer Counter XOSC FDPLL96M POWER MANAGER CLOCK CONTROLLER RESET CONTROLLER SLEEP CONTROLLER EVENT SYSTEM DMA RESETN PAD0 P
PAGE 18
SAM D21 Family Pinout Pinout 5.1 SAM D21J 5.1.1 QFN64 / TQFP64 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PB03 PB02 PB01 PB00 PB31 PB30 PA31 PA30 VDDIN VDDCORE GND PA28 RESET PA27 PB23 PB22 5.
PAGE 20
SAM D21 Family Pinout SAM D21G 5.2.1 QFN48 / TQFP48 48 47 46 45 44 43 42 41 40 39 38 37 PB03 PB02 PA31 PA30 VDDIN VDDCORE GND PA28 RESET PA27 PB23 PB22 5.
PAGE 22
SAM D21 Family Pinout SAM D21GxL 5.3.1 QFN48 48 47 46 45 44 43 42 41 40 39 38 37 PB03 PB02 PB01 PB00 PA31 PA30 VDDIN VDDCORE GND PA28 RESETN PA27 5.
PAGE 23
SAM D21 Family Pinout SAM D21ExA/B/C/D 5.4.1 QFN32 / TQFP32 32 31 30 29 28 27 26 25 PA31 PA30 VDDIN VDDCORE GND PA28 RESET PA27 5.4 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 PA25 PA24 PA23 PA22 PA19 PA18 PA17 PA16 VDDANA GND PA08 PA09 PA10 PA11 PA14 PA15 9 10 11 12 13 14 15 16 PA00 PA01 PA02 PA03 PA04 PA05 PA06 PA07 DIGITAL PIN ANALOG PIN OSCILLATOR GROUND INPUT SUPPLY REGULATED OUTPUT SUPPLY RESET PIN © 2018 Microchip Technology Inc.
PAGE 24
SAM D21 Family Pinout 5.4.2 WLCSP35 A 1 0 PA 2 0 PA 0 1 A 3 D GN 4 D VD AN A B C 30 PA CO DD RE SE 25 PA 27 PA 24 PA 02 PA 03 PA D GN 2 PA 2 23 PA 0 PA VD N DI T D GN 28 PA 6 6 V F VD 0 PA 0 PA RE E 31 PA AN 5 D 4 0 PA 5 11 PA 17 PA 19 PA 7 08 PA 09 PA 1 PA 6 18 PA 0 D GN 1 PA 4 1 PA O DI © 2018 Microchip Technology Inc.
PAGE 25
SAM D21 Family Pinout SAM D21ExL 5.5.1 QFN32 / TQFP32 32 31 30 29 28 27 26 25 PB03 PB02 PA31 PA30 VDDIO VDDCORE GND RESETN 5.5 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 PA25 PA24 PA23 PA22 PA19 PA18 PA17 PA16 VDDIO/ANA GND PA08 PA09 PA10 PA11 PA14 PA15 9 10 11 12 13 14 15 16 PA02 PA03 PB04 PB05 PA04 PA05 PA06 PA07 Digital Pin Analog Pin Oscillator Pin Ground Input Supply Regulated Output Supply Reset Pin © 2018 Microchip Technology Inc.
PAGE 26
SAM D21 Family Signal Descriptions List 6. Signal Descriptions List The following table gives details on signal names classified by peripheral.
PAGE 27
SAM D21 Family Signal Descriptions List ...........
PAGE 28
SAM D21 Family I/O Multiplexing and Considerations 7. I/O Multiplexing and Considerations 7.1 Multiplexed Signals Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one.
PAGE 29
SAM D21 Family I/O Multiplexing and Considerations ...........
PAGE 30
SAM D21 Family I/O Multiplexing and Considerations ...........continued Pin(1) SAMD21E I/O Pin SAMD21G Supply B(2)(3) A SAMD21J EIC REF ADC AC C PTC SERCOM(2)(3) DAC D E F G SERCOM-ALT TC(4) TCC COM /TCC 48 64 1. 2. 3. 4. 5. 6. PB03 VDDANA EXTINT[3] AIN[11] Y[9] SERCOM5/ PAD[1] TC6/WO[1] H AC/ GCLK TCC3/ WO[3] Use the SAMD21J pinout muxing for WLCSP45 package. All analog pin functions are on peripheral function B.
PAGE 31
SAM D21 Family I/O Multiplexing and Considerations ...........
PAGE 32
SAM D21 Family I/O Multiplexing and Considerations 37. Electrical Characteristics 7.2 Other Functions 7.2.1 Oscillator Pinout The oscillators are not mapped to the normal port functions and their multiplexing are controlled by registers in the System Controller (SYSCTRL). Table 7-3. Oscillator Pinout Oscillator Supply Signal I/O Pin XOSC VDDIO XIN PA14 XOUT PA15 XIN32 PA00 XOUT32 PA01 XOSC32K 7.2.
PAGE 33
SAM D21 Family I/O Multiplexing and Considerations 7.2.4 GPIO Clusters Table 7-6.
PAGE 34
SAM D21 Family I/O Multiplexing and Considerations ...........continued PACKAGE CLUSTER 32pins 7.2.
PAGE 35
SAM D21 Family Power Supply and Start-Up Considerations AC PA[7:2] PB[9:0] VDDIN VDDANA ADC VDDIO Power Domain Overview GND 8.1 VDDCORE Power Supply and Start-Up Considerations GNDANA 8. VOLTAGE REGULATOR OSC8M PB[31:10] PA[13:8] BOD12 XOSC AC1 PA[15:14] PA[31:16] DAC PTC Digital Logic PA[1:0] (CPU, peripherals) XOSC32K POR DFLL48M OSC32K OSCULP32K 8.2 Power Supply Considerations 8.2.
PAGE 36
SAM D21 Family Power Supply and Start-Up Considerations For decoupling recommendations for the different power supplies. Refer to Schematic Checklist for details. Related Links 42. Schematic Checklist 8.2.2 Voltage Regulator The voltage regulator has two different modes: • • 8.2.3 Normal mode: To be used when the CPU and peripherals are running Low Power (LP) mode: To be used when the regulator draws small static current.
PAGE 37
SAM D21 Family Power Supply and Start-Up Considerations 8.2.4.2 Maximum Rise Rate The rise rate of the power supply must not exceed the values described in Electrical Characteristics. Refer to the Electrical Characteristics for details. Related Links 37. Electrical Characteristics 8.3 Power-Up This section summarizes the power-up sequence of the device. The behavior after power-up is controlled by the Power Manager. Refer to PM – Power Manager for details. Related Links 16. PM – Power Manager 8.3.
PAGE 38
SAM D21 Family Power Supply and Start-Up Considerations • • BOD33: Brown-Out Detector on VDDANA BOD12: Voltage Regulator Internal Brown-Out Detector on VDDCORE. The Voltage Regulator Internal BOD is calibrated in production and its calibration configuration is stored in the NVM User Row. This configuration should not be changed if the user row is written to assure the correct behavior of the BOD12. 8.4.1 Power-On Reset on VDDANA POR monitors VDDANA.
PAGE 39
SAM D21 Family Product Mapping 9. Product Mapping Figure 9-1.
PAGE 40
SAM D21 Family Product Mapping This figure represents the full configuration of the SAM D21 with maximum Flash and SRAM capabilities and a full set of peripherals. Refer to the 2. Configuration Summary for details. © 2018 Microchip Technology Inc.
PAGE 41
SAM D21 Family Memories 10. Memories 10.1 Embedded Memories • • 10.2 Internal high-speed flash with Read-While-Write (RWW) capability on section of the array (Device Variant B, C, D, and L). Internal high-speed RAM, single-cycle access at full speed Physical Memory Map The High-Speed bus is implemented as a bus matrix. All High-Speed bus addresses are fixed, and they are never remapped in any way, even during boot. The 32-bit physical address space is mapped as follow: Table 10-1.
PAGE 42
SAM D21 Family Memories Table 10-3. RWW Section Parameters (Device Variants B, C, D,and L) Device(1) Flash size Number of pages Page size SAMD21x17 4 Kbytes 64 64 bytes SAMD21x16 2 Kbytes 32 64 bytes SAMD21x15 1 Kbytes 16 64 bytes Note: 1. x = G, J, or E. Related Links 22.8.3 PARAM 3. Ordering Information(1) 10.3 NVM Calibration and Auxiliary Space The device calibration data are stored in different sections of the NVM calibration and auxiliary space presented in the following figure.
PAGE 43
SAM D21 Family Memories To write the NVM User Row refer to NVMCTRL – Non-Volatile Memory Controller. Note that when writing to the user row the values do not get loaded by the other modules on the device until a device reset occurs. Table 10-4. NVM User Row Mapping Bit Position Name Usage 2:0 BOOTPROT Used to select one of eight different bootloader sizes. Refer to NVMCTRL – Non-Volatile Memory Controller. Default value = 7 except for WLCSP (Default value = 3).
PAGE 44
SAM D21 Family Memories ...........continued Bit Position Name Usage 41 Reserved Voltage Regulator Internal BOD(BOD12) configuration. This bit is written in production and must not be changed. Default value = 0. 47:42 Reserved 63:48 LOCK NVM Region Lock Bits. Refer to NVMCTRL – Non-Volatile Memory Controller. Default value = 0xFFFF. Related Links 22. NVMCTRL – Nonvolatile Memory Controller 17.8.14 BOD33 18.8.1 CTRL 10.3.
PAGE 45
SAM D21 Family Memories ...........continued Bit Position Name 10.3.3 73:64 Reserved 127:74 Reserved Description Serial Number Each device has a unique 128-bit serial number which is a concatenation of four 32-bit words contained at the following addresses: Word 0: 0x0080A00C Word 1: 0x0080A040 Word 2: 0x0080A044 Word 3: 0x0080A048 The uniqueness of the serial number is guaranteed only when using all 128 bits. © 2018 Microchip Technology Inc.
PAGE 46
SAM D21 Family Processor And Architecture 11. Processor And Architecture 11.1 Cortex M0+ Processor ® ® The SAM D21 implements the ARM Cortex -M0+ processor, based on the ARMv6 Architecture and ® Thumb -2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 core, and upward compatible to Cortex-M3 and M4 cores. The ARM Cortex-M0+ implemented is revision r0p1. For more information refer to http://www.arm.com. 11.1.1 Cortex M0+ Configuration Table 11-1.
PAGE 47
SAM D21 Family Processor And Architecture – • • • 11.1.3 11.1.4 The System Timer is a 24-bit timer clocked by CLK_CPU that extends the functionality of both the processor and the NVIC. Refer to the Cortex-M0+ Technical Reference Manual for details (www.arm.com). Nested Vectored Interrupt Controller (NVIC) – External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the priority of each interrupt.
PAGE 48
SAM D21 Family Processor And Architecture 11.2.2 Interrupt Line Mapping Each of the 29 interrupt lines is connected to one peripheral instance, as shown in the table below. Each peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register. The Interrupt flag is set when the Interrupt condition occurs.
PAGE 49
SAM D21 Family Processor And Architecture ...........continued Peripheral Source NVIC Line TC6 – Timer Counter 6 21 TC7 – Timer Counter 7 22 ADC – Analog-to-Digital Converter 23 AC – Analog Comparator 24 DAC – Digital-to-Analog Converter 25 PTC – Peripheral Touch Controller 26 I2S - Inter IC Sound 27 AC1 - Analog Comparator 1 28 TCC3 - Timer Counter for Control 3 29 11.3 Micro Trace Buffer 11.3.1 Features • • • • 11.3.
PAGE 50
SAM D21 Family Processor And Architecture M0+ Technical Reference Manual. The MTB has 4 programmable registers to control the behavior of the trace features: • • • • POSITION: Contains the trace write pointer and the wrap bit, MASTER: Contains the main trace enable bit and other trace control fields, FLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits, BASE: Indicates where the SRAM is located in the processor memory map.
PAGE 51
SAM D21 Family Processor And Architecture Table 11-4. Bus Matrix Masters Bus Matrix Masters Master ID CM0+ - Cortex M0+ Processor 0 DSU - Device Service Unit 1 DMAC - Direct Memory Access Controller / Data Access 2 Table 11-5. Bus Matrix Slaves Bus Matrix Slaves Slave ID Internal Flash Memory 0 AHB-APB Bridge A 1 AHB-APB Bridge B 2 AHB-APB Bridge C 3 SRAM Port 4 - CM0+ Access 4 SRAM Port 5 - DMAC Data Access 5 SRAM Port 6 - DSU Access 6 Table 11-6. SRAM Port Connection 11.4.
PAGE 52
SAM D21 Family Processor And Architecture ...........continued Value Name Description 10 MEDIUM Sensitive Latency 11 HIGH Critical Latency If a master is configured with QoS level 0x00 or 0x01 there will be minimum one cycle latency for the RAM access. The priority order for concurrent accesses are decided by two factors. First the QoS level for the master and then a static priority given by table nn-mm (table: SRAM port connection) where the lowest port ID has the highest static priority.
PAGE 53
SAM D21 Family Processor And Architecture Figure 11-1. APB Write Access. T0 T1 T2 T3 PCLK T0 T1 T2 T3 T4 T5 T4 T5 PCLK PADDR Addr 1 PADDR PWRITE PWRITE PSEL PSEL PENABLE PENABLE PWDATA Addr 1 PWDATA Data 1 PREADY Data 1 PREADY No wait states Wait states Figure 11-2. APB Read Access.
PAGE 54
SAM D21 Family Processor And Architecture debugger makes an access to a peripheral, write-protection is ignored so that the debugger can update the register. Write-protect registers allow the user to disable a selected peripheral’s write-protection without doing a read-modify-write operation. These registers are mapped into two I/O memory locations, one for clearing and one for setting the register bits.
PAGE 55
SAM D21 Family Processor And Architecture 11.6.2.1.1 Write Protect Clear Name: Offset: Reset: Property: Bit WPCLR 0x00 0x000000 – 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 0 Access Reset Bit Access Reset Bit Access Reset Bit 7 Access Reset 6 5 4 3 2 1 EIC RTC WDT GCLK SYSCTRL PM R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bit 6 – EIC Writing a zero to these bits has no effect.
PAGE 56
SAM D21 Family Processor And Architecture Value 0 1 Description Write-protection is disabled. Write-protection is enabled. Bit 3 – GCLK Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals. Value 0 1 Description Write-protection is disabled. Write-protection is enabled. Bit 2 – SYSCTRL Writing a zero to these bits has no effect.
PAGE 57
SAM D21 Family Processor And Architecture 11.6.2.1.2 Write Protect Set Name: Offset: Reset: Property: Bit WPSET 0x04 0x000000 – 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 0 Access Reset Bit Access Reset Bit Access Reset Bit 7 Access Reset 6 5 4 3 2 1 EIC RTC WDT GCLK SYSCTRL PM R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bit 6 – EIC Writing a zero to these bits has no effect.
PAGE 58
SAM D21 Family Processor And Architecture Value 0 1 Description Write-protection is disabled. Write-protection is enabled. Bit 3 – GCLK Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals. Value 0 1 Description Write-protection is disabled. Write-protection is enabled. Bit 2 – SYSCTRL Writing a zero to these bits has no effect.
PAGE 59
SAM D21 Family Processor And Architecture 11.6.2.2.1 Write Protect Clear Name: Offset: Reset: Property: Bit WPCLR 0x00 0x000002 – 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 0 Access Reset Bit Access Reset Bit Access Reset Bit 7 Access Reset 6 5 4 3 2 1 MTB USB DMAC PORT NVMCTRL DSU R/W R/W R/W R/W R/W R/W 0 0 0 0 0 1 Bit 6 – MTB Writing a zero to these bits has no effect.
PAGE 60
SAM D21 Family Processor And Architecture Value 0 1 Description Write-protection is disabled. Write-protection is enabled. Bit 3 – PORT Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals. Value 0 1 Description Write-protection is disabled. Write-protection is enabled. Bit 2 – NVMCTRL Writing a zero to these bits has no effect.
PAGE 61
SAM D21 Family Processor And Architecture 11.6.2.2.2 Write Protect Set Name: Offset: Reset: Property: Bit WPSET 0x04 0x000002 – 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 0 Access Reset Bit Access Reset Bit Access Reset Bit 7 Access Reset 6 5 4 3 2 1 MTB USB DMAC PORT NVMCTRL DSU R/W R/W R/W R/W R/W R/W 0 0 0 0 0 1 Bit 6 – MTB Writing a zero to these bits has no effect.
PAGE 62
SAM D21 Family Processor And Architecture Value 0 1 Description Write-protection is disabled. Write-protection is enabled. Bit 3 – PORT Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals. Value 0 1 Description Write-protection is disabled. Write-protection is enabled. Bit 2 – NVMCTRL Writing a zero to these bits has no effect.
PAGE 63
SAM D21 Family Processor And Architecture 11.6.2.3.
PAGE 64
SAM D21 Family Processor And Architecture Value 0 1 Description Write protection is disabled Write protection is enabled Bit 19 – PTC Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals. Value 0 1 Description Write protection is disabled Write protection is enabled Bit 18 – DAC Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals.
PAGE 65
SAM D21 Family Processor And Architecture Value 0 1 Description Write protection is disabled Write protection is enabled Bits 7:2 – SERCOM[5:0] Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals. Value 0 1 Description Write protection is disabled Write protection is enabled Bit 1 – EVSYS Writing a zero to these bits has no effect.
PAGE 66
SAM D21 Family Processor And Architecture 11.6.2.3.
PAGE 67
SAM D21 Family Processor And Architecture Value 0 1 Description Write protection is disabled Write protection is enabled Bit 19 – PTC Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals. Value 0 1 Description Write protection is disabled Write protection is enabled Bit 18 – DAC Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals.
PAGE 68
SAM D21 Family Processor And Architecture Value 0 1 Description Write protection is disabled Write protection is enabled Bits 2, 3, 4, 5, 6, 7 – SERCOM Writing a zero to these bits has no effect. Writing a one to these bits will clear the Write-Protect bit for the corresponding peripherals. Value 0 1 Description Write protection is disabled Write protection is enabled Bit 1 – EVSYS Writing a zero to these bits has no effect.
PAGE 69
SAM D21 Family Peripherals Configuration Summary 12. Peripherals Configuration Summary Table 12-1. Peripherals Configuration Summary Periph. Base IRQ AHB Clock Name Address Line Index Enabled Index Enabled Index APB Clock at Reset AHB-APB 0x40000000 Bridge A 0 Generic Clock PAC Events Index Prot.
PAGE 70
SAM D21 Family Peripherals Configuration Summary ...........continued Periph. Base IRQ AHB Clock Name Address Line Index Enabled Index Enabled Index APB Clock at Reset Generic Clock PAC Events Index Prot.
PAGE 71
SAM D21 Family DSU - Device Service Unit 13. DSU - Device Service Unit 13.1 Overview The Device Service Unit (DSU) provides a means of detecting debugger probes. It enables the ARM Debug Access Port (DAP) to have control over multiplexed debug pads and CPU reset. The DSU also provides system-level services to debug adapters in an ARM debug system. It implements a CoreSight Debug ROM that provides device identification as well as identification of other debug components within the system.
PAGE 72
SAM D21 Family DSU - Device Service Unit 13.3 Block Diagram Figure 13-1. DSU Block Diagram DSU RESET SWCLK debugger_present DEBUGGER PROBE INTERFACE cpu_reset_extension CPU DAP AHB-AP DAP SECURITY FILTER NVMCTRL DBG CORESIGHT ROM PORT S M CRC-32 SWDIO MBIST M HIGH-SPEED BUS MATRIX CHIP ERASE 13.4 Signal Description The DSU uses three signals to function.
PAGE 73
SAM D21 Family DSU - Device Service Unit Related Links 16. PM – Power Manager 13.5.3 Clocks The DSU bus clocks (CLK_DSU_APB and CLK_DSU_AHB) can be enabled and disabled by the Power Manager. Refer to PM – Power Manager Related Links 16. PM – Power Manager 13.5.4 DMA Not applicable. 13.5.5 Interrupts Not applicable. 13.5.6 Events Not applicable. 13.5.
PAGE 74
SAM D21 Family DSU - Device Service Unit the system. The debugger is detected on a RESET release event when SWCLK is low. At startup, SWCLK is internally pulled up to avoid false detection of a debugger if the SWCLK pin is left unconnected. When the CPU is held in the reset extension phase, the CPU Reset Extension bit of the Status A register (STATUSA.CRSTEXT) is set. To release the CPU, write a '1' to STATUSA.CRSTEXT. STATUSA.CRSTEXT will then be set to '0'. Writing a '0' to STATUSA.CRSTEXT has no effect.
PAGE 75
SAM D21 Family DSU - Device Service Unit Figure 13-3. Hot-Plugging Detection Timing Diagram SWCLK RESET CPU_STATE reset running Hot-Plugging The presence of a debugger probe is detected when either Hot-Plugging or Cold-Plugging is detected. Once detected, the Debugger Present bit of the Status B register (STATUSB.DBGPRES) is set. For security reasons, Hot-Plugging is not available when the device is protected by the NVMCTRL security bit. This detection requires that pads are correctly powered.
PAGE 76
SAM D21 Family DSU - Device Service Unit 2.2. 3. 4. 13.8 Erases the whole Flash array (including the EEPROM emulation area, not including auxiliary rows). 2.3. Erases the lock row, removing the NVMCTRL security bit protection. Check for completion by polling STATUSA.DONE (read as '1' when completed). Reset the device to let the NVMCTRL update the fuses. Programming Programming the Flash or RAM memories is only possible when the device is not protected by the NVMCTRL security bit.
PAGE 77
SAM D21 Family DSU - Device Service Unit • • Internally from the CPU, without any limitation, even when the device is protected Externally from a debug adapter, with some restrictions when the device is protected For security reasons, DSU features have limitations when used from a debug adapter.
PAGE 78
SAM D21 Family DSU - Device Service Unit 22. NVMCTRL – Nonvolatile Memory Controller 22.6.6 Security Bit 13.10 Device Identification Device identification relies on the ARM CoreSight component identification scheme, which allows the chip to be identified as a SAM device implementing a DSU. The DSU contains identification registers to differentiate the device. 13.10.
PAGE 79
SAM D21 Family DSU - Device Service Unit • • 13.11 Product series identification Device select Functional Description 13.11.1 Principle of Operation The DSU provides memory services, such as CRC32 or MBIST that require almost the same interface. Hence, the Address, Length and Data registers (ADDR, LENGTH, DATA) are shared. These shared registers must be configured first; then a command can be issued by writing the Control register.
PAGE 80
SAM D21 Family DSU - Device Service Unit ...........continued AMOD[1:0] Short name External range restrictions 1 EEPROM 2-3 Reserved CRC32 of the whole EEPROM emulation area DATA forced to 0xFFFFFFFF before calculation (no seed) The algorithm employed is the industry standard CRC32 algorithm using the generator polynomial 0xEDB88320 (reversed representation). 13.11.3.
PAGE 81
SAM D21 Family DSU - Device Service Unit Related Links 22. NVMCTRL – Nonvolatile Memory Controller 22.6.6 Security Bit 13.11.5 Testing of On-Board Memories MBIST The DSU implements a feature for automatic testing of memory, also known as MBIST (memory built-in self test). This is primarily intended for production test of on-board memories. MBIST cannot be operated from the external address range when the device is protected by the NVMCTRL security bit.
PAGE 82
SAM D21 Family DSU - Device Service Unit writing a '1' in STATUSA.FAIL to resume. Prior to resuming, user can read the DATA and ADDR registers to locate the fault. Locating Faults If the test stops with STATUSA.FAIL set, one or more bits failed the test. The test stops at the first detected error. The position of the failing bit can be found by reading the following registers: 4.
PAGE 83
SAM D21 Family DSU - Device Service Unit ...........continued AMOD[1:0] Description 0x2, 0x3 Reserved Related Links 22. NVMCTRL – Nonvolatile Memory Controller 22.6.6 Security Bit 9. Product Mapping 13.11.6 System Services Availability when Accessed Externally and Device is Protected External access: Access performed in the DSU address offset 0x200-0x1FFF range. Internal access: Access performed in the DSU address offset 0x000-0x100 range. Table 13-6.
PAGE 84
SAM D21 Family DSU - Device Service Unit 13.12 Register Summary Offset Name Bit Pos.
PAGE 85
SAM D21 Family DSU - Device Service Unit ...........continued Offset Name Bit Pos. 0x100C ... Reserved 0x1FCB 7:0 0x1FCC MEMTYPE SMEMP 15:8 23:16 31:24 7:0 0x1FD0 PID4 FKBC[3:0] JEPCC[3:0] 15:8 23:16 31:24 0x1FD4 ...
PAGE 86
SAM D21 Family DSU - Device Service Unit ...........continued Offset Name Bit Pos. 7:0 0x1FFC CID3 PREAMBLEB3[7:0] 15:8 23:16 31:24 13.13 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC).
PAGE 87
SAM D21 Family DSU - Device Service Unit 13.13.1 Control Name: Offset: Reset: Property: Bit 7 CTRL 0x0000 0x00 PAC Write-Protection 6 5 4 3 2 CE MBIST CRC 1 SWRST 0 Access W W W W Reset 0 0 0 0 Bit 4 – CE Chip-Erase Writing a '0' to this bit has no effect. Writing a '1' to this bit starts the Chip-Erase operation. Bit 3 – MBIST Memory Built-In Self-Test Writing a '0' to this bit has no effect. Writing a '1' to this bit starts the memory BIST algorithm.
PAGE 88
SAM D21 Family DSU - Device Service Unit 13.13.2 Status A Name: Offset: Reset: Property: Bit 7 STATUSA 0x0001 0x00 PAC Write-Protection 6 5 Access 4 3 2 1 0 PERR FAIL BERR CRSTEXT DONE R/W R/W R/W R/W R/W 0 0 0 0 0 Reset Bit 4 – PERR Protection Error Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Protection Error bit. This bit is set when a command that is not allowed in protected state is issued.
PAGE 89
SAM D21 Family DSU - Device Service Unit 13.13.3 Status B Name: Offset: Reset: Property: Bit 7 STATUSB 0x0002 0x1X PAC Write-Protection 6 5 4 3 2 1 0 HPE DCCD1 DCCD0 DBGPRES PROT Access R R R R R Reset 1 0 0 0 0 Bit 4 – HPE Hot-Plugging Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set when Hot-Plugging is enabled. This bit is cleared when Hot-Plugging is disabled. This is the case when the SWCLK function is changed.
PAGE 90
SAM D21 Family DSU - Device Service Unit 13.13.
PAGE 91
SAM D21 Family DSU - Device Service Unit 13.13.
PAGE 92
SAM D21 Family DSU - Device Service Unit 13.13.
PAGE 93
SAM D21 Family DSU - Device Service Unit 13.13.
PAGE 94
SAM D21 Family DSU - Device Service Unit 13.13.
PAGE 95
SAM D21 Family DSU - Device Service Unit 13.13.9 Device Identification Name: Offset: Property: DID 0x0018 PAC Write-Protection The information in this register is related to the Ordering Information.
PAGE 96
SAM D21 Family DSU - Device Service Unit 13.13.
PAGE 97
SAM D21 Family DSU - Device Service Unit 13.13.
PAGE 98
SAM D21 Family DSU - Device Service Unit 13.13.
PAGE 99
SAM D21 Family DSU - Device Service Unit 13.13.13 CoreSight ROM Table Memory Type Name: Offset: Reset: Property: Bit MEMTYPE 0x1FCC 0x0000000x - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit SMEMP Access R Reset x Bit 0 – SMEMP System Memory Present This bit indicates whether system memory is present on the bus that connects to the ROM table.
PAGE 100
SAM D21 Family DSU - Device Service Unit 13.13.
PAGE 101
SAM D21 Family DSU - Device Service Unit 13.13.
PAGE 102
SAM D21 Family DSU - Device Service Unit 13.13.
PAGE 103
SAM D21 Family DSU - Device Service Unit 13.13.17 Peripheral Identification 2 Name: Offset: Reset: Property: Bit PID2 0x1FE8 0x00000009 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Bit 7 6 5 4 3 2 1 0 Access R R R R R R R R Reset 0 0 0 0 1 0 0 1 Access Reset Bit Access Reset Bit Access Reset REVISION[3:0] JEPU JEPIDCH[2:0] Bits 7:4 – REVISION[3:0] Revision Number Revision of the peripheral.
PAGE 104
SAM D21 Family DSU - Device Service Unit 13.13.18 Peripheral Identification 3 Name: Offset: Reset: Property: Bit PID3 0x1FEC 0x00000000 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Bit 7 6 5 4 3 2 1 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Access Reset Bit Access Reset Bit Access Reset REVAND[3:0] CUSMOD[3:0] Bits 7:4 – REVAND[3:0] Revision Number These bits will always return 0x0 when read.
PAGE 105
SAM D21 Family DSU - Device Service Unit 13.13.19 Component Identification 0 Name: Offset: Reset: Property: Bit CID0 0x1FF0 0x0000000D - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Bit 7 6 5 4 3 2 1 0 Access R R R R R R R R Reset 0 0 0 0 1 1 0 1 Access Reset Bit Access Reset Bit Access Reset PREAMBLEB0[7:0] Bits 7:0 – PREAMBLEB0[7:0] Preamble Byte 0 These bits will always return 0x0000000D when read.
PAGE 106
SAM D21 Family DSU - Device Service Unit 13.13.
PAGE 107
SAM D21 Family DSU - Device Service Unit 13.13.21 Component Identification 2 Name: Offset: Reset: Property: Bit CID2 0x1FF8 0x00000005 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Bit 7 6 5 4 3 2 1 0 Access R R R R R R R R Reset 0 0 0 0 0 1 0 1 Access Reset Bit Access Reset Bit Access Reset PREAMBLEB2[7:0] Bits 7:0 – PREAMBLEB2[7:0] Preamble Byte 2 These bits will always return 0x00000005 when read.
PAGE 108
SAM D21 Family DSU - Device Service Unit 13.13.22 Component Identification 3 Name: Offset: Reset: Property: Bit CID3 0x1FFC 0x000000B1 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Bit 7 6 5 4 3 2 1 0 Access R R R R R R R R Reset 1 0 1 1 0 0 0 1 Access Reset Bit Access Reset Bit Access Reset PREAMBLEB3[7:0] Bits 7:0 – PREAMBLEB3[7:0] Preamble Byte 3 These bits will always return 0x000000B1 when read.
PAGE 109
SAM D21 Family Clock System 14. Clock System This chapter summarizes the clock distribution and terminology in the SAM D21 device. It will not explain every detail of its configuration. For in-depth documentation, see the respective peripherals descriptions and the Generic Clock documentation. Related Links 15. GCLK - Generic Clock Controller 14.1 Clock Distribution Figure 14-1.
PAGE 110
SAM D21 Family Clock System SERCOM0. The SERCOM0 interface, clocked by CLK_SERCOM0_APB, has been unmasked in the APBC Mask register in the PM. Figure 14-2. Example of SERCOM clock PM Synchronous Clock Controller SYSCTRL DFLL48M 14.2 CLK_SERCOM0_APB GCLK Generic Clock Generator 1 Generic Clock Multiplexer 20 GCLK_SERCOM0_CORE SERCOM 0 Synchronous and Asynchronous Clocks As the CPU and the peripherals can be in different clock domains, i.e.
PAGE 111
SAM D21 Family Clock System Each individual register description will have the properties "Read-Synchronized" and/or "WriteSynchronized" if a register is synchronized. As shown in the figure below, the common synchronizer is used for all registers in one peripheral. Therefore, status register (STATUS) of each peripheral can be synchronized at a time. Figure 14-3.
PAGE 112
SAM D21 Family Clock System • • • Writing a generic clock peripheral core register Reading a read-synchronized peripheral core register Reading the register that is being written (and thus triggered the synchronization) Peripheral core registers without read-synchronization will remain static once they have been written and synchronized, and can be read while the synchronization is ongoing without causing the peripheral bus to stall.
PAGE 113
SAM D21 Family Clock System 14.3.1.6 Enable Write-Synchronization Writing to the Enable bit in the Control register (CTRL.ENABLE) will also trigger write-synchronization and set STATUS.SYNCBUSY. CTRL.ENABLE will read its new value immediately after being written. The Synchronisation Ready interrupt (if available) cannot be used for Enable write-synchronization. When the enable write-synchronization is ongoing (STATUS.
PAGE 114
SAM D21 Family Clock System 14.3.2.2 General Write synchronization Write-Synchronization is triggered by writing to a register in the peripheral clock domain. The respective bit in the Synchronization Busy register (SYNCBUSY) will be set when the write-synchronization starts and cleared when the write-synchronization is complete. Refer to 14.3.2.7 Synchronization Delay for details on the synchronization delay.
PAGE 115
SAM D21 Family Clock System 14.3.2.7 Synchronization Delay The synchronization will delay write and read accesses by a certain amount. This delay D is within the range of: 5 × �GCLK + 2 × �APB < � < 6 × �GCLK + 3 × �APB Where �GCLK is the period of the generic clock and �APB is the period of the peripheral bus clock. A normal peripheral bus register access duration is 2 × �APB. 14.
PAGE 116
SAM D21 Family Clock System frequency as well as the divider used in the Generic Clock Generator.
PAGE 117
SAM D21 Family GCLK - Generic Clock Controller 15. GCLK - Generic Clock Controller 15.1 Overview Depending on the application, peripherals may require specific clock frequencies to operate correctly. The Generic Clock controller GCLK provides nine Generic Clock Generators that can provide a wide range of clock frequencies. Generators can be set to use different external and internal oscillators as source. The clock of each Generator can be divided.
PAGE 118
SAM D21 Family GCLK - Generic Clock Controller Figure 15-2.
PAGE 119
SAM D21 Family GCLK - Generic Clock Controller 15.5.2 Power Management The GCLK can operate in sleep modes, if required. Refer to the sleep mode description in the Power Manager (PM) section. Related Links 16. PM – Power Manager 15.5.3 Clocks The GCLK bus clock (CLK_GCLK_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_GCLK_APB can be found in the Peripheral Clock Masking section of PM – Power Manager. Related Links 16. PM – Power Manager 15.5.4 DMA Not applicable.
PAGE 120
SAM D21 Family GCLK - Generic Clock Controller 15.6.2 Basic Operation 15.6.2.1 Initialization Before a Generator is enabled, the corresponding clock source should be enabled. The Peripheral clock must be configured as outlined by the following steps: 1. 2. 3.
PAGE 121
SAM D21 Family GCLK - Generic Clock Controller Refer to PM-Power Manager for details on the synchronous clock generation. Figure 15-3. Generic Clock Generator GCLKGENSRC Clock Sources 0 GCLKGENSRC DIVIDER Clock Gate GCLKGEN[x] 1 GCLK_IO[x] GENCTRL.GENEN GENCTRL.SRC GENCTRL.DIVSEL GENDIV.DIV Related Links 16. PM – Power Manager 15.6.2.
PAGE 122
SAM D21 Family GCLK - Generic Clock Controller 15.6.2.9 Generic Clock Output on I/O Pins Each Generator's output can be directed to a GCLK_IO pin. If the Output Enable bit in GENCTRL is '1' (GENCTRL.OE=1) and the Generator is enabled (GENCTRL.GENEN=1), the Generator requests its clock source and the GCLKGEN clock is output to a GCLK_IO pin. If GENCTRL.OE=0, GCLK_IO is set according to the Output Off Value bit. If the Output Off Value bit in GENCTRL (GENCTRL.
PAGE 123
SAM D21 Family GCLK - Generic Clock Controller 15.6.3.4 Configuration Lock The generic clock configuration can be locked for further write accesses by setting the Write Lock bit in the CLKCTRL register (CLKCTRL.WRTLOCK). All writes to the CLKCTRL register will be ignored. It can only be unlocked by a Power Reset. The Generator source of a locked generic clock are also locked, too: The corresponding GENCTRL and GENDIV are locked, and can be unlocked only by a Power Reset.
PAGE 124
SAM D21 Family GCLK - Generic Clock Controller 15.6.5 Sleep Mode Operation 15.6.5.1 Sleep Walking The GCLK module supports the Sleep Walking feature. If the system is in a sleep mode where the Generic Clocks are stopped, a peripheral that needs its clock in order to execute a process must request it from the Generic Clock Controller. The Generic Clock Controller receives this request, determines which Generic Clock Generator is involved and which clock source needs to be awakened.
PAGE 125
SAM D21 Family GCLK - Generic Clock Controller 15.7 Register Summary Offset Name Bit Pos. 0x00 CTRL 7:0 0x01 STATUS 7:0 0x02 CLKCTRL SWRST SYNCBUSY 7:0 15:8 ID[5:0] WRTLOCK CLKEN GEN[3:0] 7:0 0x04 GENCTRL ID[3:0] 15:8 23:16 SRC[4:0] RUNSTDBY DIVSEL OE OOV IDC GENEN 31:24 7:0 0x08 GENDIV ID[3:0] 15:8 DIV[7:0] 23:16 DIV[15:8] 31:24 15.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported.
PAGE 126
SAM D21 Family GCLK - Generic Clock Controller 15.8.1 Control Name: Offset: Reset: Property: Bit 7 CTRL 0x0 0x00 Write-Protected, Write-Synchronized 6 5 4 3 2 1 0 SWRST Access R/W Reset 0 Bit 0 – SWRST Software Reset Writing a zero to this bit has no effect. Writing a one to this bit resets all registers in the GCLK to their initial state after a power reset, except for generic clocks and associated generators that have their WRTLOCK bit in CLKCTRL read as one. Refer to GENCTRL.
PAGE 127
SAM D21 Family GCLK - Generic Clock Controller 15.8.2 Status Name: Offset: Reset: Property: Bit 7 STATUS 0x1 0x00 - 6 5 4 3 2 1 0 SYNCBUSY Access R Reset 0 Bit 7 – SYNCBUSY Synchronization Busy Status This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. © 2018 Microchip Technology Inc.
PAGE 128
SAM D21 Family GCLK - Generic Clock Controller 15.8.3 Generic Clock Control Name: Offset: Reset: Property: Bit CLKCTRL 0x2 0x0000 Write-Protected 15 14 WRTLOCK CLKEN Access 13 12 11 10 9 8 GEN[3:0] R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 2 1 0 5 4 3 ID[5:0] Access Reset R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bit 15 – WRTLOCK Write Lock When this bit is written, it will lock from further writes the generic clock pointed to by CLKCTRL.
PAGE 129
SAM D21 Family GCLK - Generic Clock Controller ...........continued GEN[3:0] Name Description 0x6 GCLKGEN6 Generic clock generator 6 0x7 GCLKGEN7 Generic clock generator 7 0x8 GCLKGEN8 Generic clock generator 8 0x9-0xF - Reserved Bits 5:0 – ID[5:0] Generic Clock Selection ID These bits select the generic clock that will be configured. The value of the ID bit group versus module instance is shown in the table below. A Power Reset will reset the CLKCTRL register for all IDs, including the RTC.
PAGE 130
SAM D21 Family GCLK - Generic Clock Controller ...........continued Module Instance Reset Value after a User Reset CLKCTRL.GEN CLCTRL.CLKEN CLKCTRL.
PAGE 131
SAM D21 Family GCLK - Generic Clock Controller Value 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26-0x 3F Name GCLK_AC_DIG, GCLK_AC1_DIG GCLK_AC_ANA, GCLK_AC1_ANA GCLK_DAC GCLK_PTC GCLK_I2S_0 GCLK_I2S_1 GCLK_TCC3 - © 2018 Microchip Technology Inc.
PAGE 132
SAM D21 Family GCLK - Generic Clock Controller 15.8.
PAGE 133
SAM D21 Family GCLK - Generic Clock Controller Bit 19 – OE Output Enable This bit is used to enable output of the generated clock to GCLK_IO when GCLK_IO is not selected as a source in the GENCLK.SRC bit group. Value 0 1 Description The generic clock generator is not output. The generic clock generator is output to the corresponding GCLK_IO, unless the corresponding GCLK_IO is selected as a source in the GENCLK.SRC bit group.
PAGE 134
SAM D21 Family GCLK - Generic Clock Controller Bits 3:0 – ID[3:0] Generic Clock Generator Selection These bits select the generic clock generator that will be configured or read. The value of the ID bit group versus which generic clock generator is configured is shown in the next table. A power reset will reset the GENCTRL register for all IDs, including the generic clock generator used by the RTC.
PAGE 135
SAM D21 Family GCLK - Generic Clock Controller ...........
PAGE 136
SAM D21 Family GCLK - Generic Clock Controller 15.8.
PAGE 137
SAM D21 Family GCLK - Generic Clock Controller ...........continued Values Description 0x3 Generic clock generator 3 0x4 Generic clock generator 4 0x5 Generic clock generator 5 0x6 Generic clock generator 6 0x7 Generic clock generator 7 0x8 Generic clock generator 8 0x9-0xF Reserved A power reset will reset the GENDIV register for all IDs, including the generic clock generator used by the RTC.
PAGE 138
SAM D21 Family GCLK - Generic Clock Controller ...........
PAGE 139
SAM D21 Family PM – Power Manager 16. 16.1 PM – Power Manager Overview The Power Manager (PM) controls the reset, clock generation and sleep modes of the device. Utilizing a main clock chosen from a large number of clock sources from the GCLK, the clock controller provides synchronous system clocks to the CPU and the modules connected to the AHB and the APBx bus. The synchronous system clocks are divided into a number of clock domains; one for the CPU and AHB and one for each APBx.
PAGE 140
SAM D21 Family PM – Power Manager 16.3 Block Diagram Figure 16-1. PM Block Diagram POWER MANAGER CLK_APB GCLK SYNCHRONOUS CLOCK CONTROLLER CLK_AHB PERIPHERALS CLK_CPU SLEEP MODE CONTROLLER CPU BOD12 USER RESET BOD33 POWER RESET POR RESET CONTROLLER WDT CPU RESET RESET SOURCES 16.4 Signal Description Signal Name Type Description RESET Digital input External reset Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral.
PAGE 141
SAM D21 Family PM – Power Manager 16.5.3 Clocks The PM bus clock (CLK_PM_APB) can be enabled and disabled in the Power Manager, and the default state of CLK_PM_APB can be found in Peripheral Clock Default State table in the Peripheral Clock Masking section. If this clock is disabled in the Power Manager, it can only be re-enabled by a reset. A generic clock (GCLK_MAIN) is required to generate the main clock.
PAGE 142
SAM D21 Family PM – Power Manager 16.5.8 Register Access Protection Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following: • • Interrupt Flag register (INTFLAG). Reset Cause register (RCAUSE). Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger.
PAGE 143
SAM D21 Family PM – Power Manager 16.6.2.2 Enabling, Disabling and Resetting The PM module is always enabled and can not be reset. 16.6.2.3 Selecting the Main Clock Source Refer to GCLK – Generic Clock Controller for details on how to configure the main clock source. Related Links 15. GCLK - Generic Clock Controller 16.6.2.4 Selecting the Synchronous Clock Division Ratio The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks.
PAGE 144
SAM D21 Family PM – Power Manager Figure 16-2.
PAGE 145
SAM D21 Family PM – Power Manager ...........
PAGE 146
SAM D21 Family PM – Power Manager Table 16-2. Effects of the Different Reset Events Power Reset User Reset POR, BOD12, BOD33 External Reset WDT Reset, SysResetReq RTC All the 32kHz sources WDT with ALWAYSON feature Generic Clock with WRTLOCK feature Y N N Debug logic Y Y N Others Y Y Y The external reset is generated when pulling the RESET pin low. This pin has an internal pull-up, and does not need to be driven externally during normal operation.
PAGE 147
SAM D21 Family PM – Power Manager 16.6.2.8 Sleep Mode Controller Sleep mode is activated by the Wait For Interrupt instruction (WFI). The Idle bits in the Sleep Mode register (SLEEP.IDLE) and the SLEEPDEEP bit of the System Control register of the CPU should be used as argument to select the level of the sleep mode. There are two main types of sleep mode: • IDLE mode: The CPU is stopped. Optionally, some synchronous clock domains are stopped, depending on the IDLE argument.
PAGE 148
SAM D21 Family PM – Power Manager • IDLE mode, the user must configure the IDLE mode configuration bit group and must write a zero to the SCR.SLEEPDEEP bit. Exiting IDLE mode: The processor wakes the system up when it detects the occurrence of any interrupt that is not masked in the NVIC Controller with sufficient priority to cause exception entry. The system goes back to the ACTIVE mode. The CPU and affected modules are restarted. 16.6.2.8.
PAGE 149
SAM D21 Family PM – Power Manager details. If the peripheral has one common interrupt request line for all the interrupt sources, the user must read the INTFLAG register to determine which interrupt condition is present. Related Links 11.2 Nested Vector Interrupt Controller 16.6.6 Events Not applicable. 16.6.7 Sleep Mode Operation In all IDLE sleep modes, the power manager is still running on the selected main clock.
PAGE 150
SAM D21 Family PM – Power Manager 16.7 Register Summary Offset Name Bit Pos. 0x00 CTRL 7:0 0x01 SLEEP 7:0 IDLE[1:0] 0x02 ... Reserved 0x07 0x08 CPUSEL 7:0 CPUDIV[2:0] 0x09 APBASEL 7:0 APBADIV[2:0] 0x0A APBBSEL 7:0 APBBDIV[2:0] 0x0B APBCSEL 7:0 APBCDIV[2:0] 0x0C ...
PAGE 151
SAM D21 Family PM – Power Manager Exception for APBASEL, APBBSEL and APBCSEL: These registers must only be accessed with 8-bit access. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description. © 2018 Microchip Technology Inc.
PAGE 152
SAM D21 Family PM – Power Manager 16.8.1 Control Name: Offset: Reset: Property: Bit 7 CTRL 0x00 0x00 Write-Protected 6 5 4 3 2 1 0 Access Reset © 2018 Microchip Technology Inc.
PAGE 153
SAM D21 Family PM – Power Manager 16.8.2 Sleep Mode Name: Offset: Reset: Property: Bit 7 SLEEP 0x01 0x00 Write-Protected 6 5 4 3 2 1 0 IDLE[1:0] Access Reset R/W R/W 0 0 Bits 1:0 – IDLE[1:0] Idle Mode Configuration These bits select the Idle mode configuration after a WFI instruction.
PAGE 154
SAM D21 Family PM – Power Manager 16.8.3 CPU Clock Select Name: Offset: Reset: Property: Bit CPUSEL 0x08 0x00 Write-Protected 7 6 5 4 3 2 1 0 CPUDIV[2:0] Access Reset R/W R/W R/W 0 0 0 Bits 2:0 – CPUDIV[2:0] CPU Prescaler Selection These bits define the division ratio of the main clock prescaler (2n).
PAGE 155
SAM D21 Family PM – Power Manager 16.8.4 APBA Clock Select Name: Offset: Reset: Property: Bit APBASEL 0x09 0x00 Write-Protected 7 6 5 4 3 2 1 0 APBADIV[2:0] Access Reset R/W R/W R/W 0 0 0 Bits 2:0 – APBADIV[2:0] APBA Prescaler Selection These bits define the division ratio of the APBA clock prescaler (2n).
PAGE 156
SAM D21 Family PM – Power Manager 16.8.5 APBB Clock Select Name: Offset: Reset: Property: Bit APBBSEL 0x0A 0x00 Write-Protected 7 6 5 4 3 2 1 0 APBBDIV[2:0] Access Reset R/W R/W R/W 0 0 0 Bits 2:0 – APBBDIV[2:0] APBB Prescaler Selection These bits define the division ratio of the APBB clock prescaler (2n).
PAGE 157
SAM D21 Family PM – Power Manager 16.8.6 APBC Clock Select Name: Offset: Reset: Property: Bit APBCSEL 0x0B 0x00 Write-Protected 7 6 5 4 3 2 1 0 APBCDIV[2:0] Access Reset R/W R/W R/W 0 0 0 Bits 2:0 – APBCDIV[2:0] APBC Prescaler Selection These bits define the division ratio of the APBC clock prescaler (2n).
PAGE 158
SAM D21 Family PM – Power Manager 16.8.7 AHB Mask Name: Offset: Reset: Property: Bit AHBMASK 0x14 0x0000007F Write-Protected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USB DMAC NVMCTRL DSU HPB2 HPB1 HPB0 R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 6 – USB USB AHB Clock Mask Value 0 1 Description The AHB clock for the USB is stopped.
PAGE 159
SAM D21 Family PM – Power Manager Bit 2 – HPB2 HPB2 AHB Clock Mask Value 0 1 Description The AHB clock for the HPB2 is stopped. The AHB clock for the HPB2 is enabled. Bit 1 – HPB1 HPB1 AHB Clock Mask Value 0 1 Description The AHB clock for the HPB1 is stopped. The AHB clock for the HPB1 is enabled. Bit 0 – HPB0 HPB0 AHB Clock Mask Value 0 1 Description The AHB clock for the HPB0 is stopped. The AHB clock for the HPB0 is enabled. © 2018 Microchip Technology Inc.
PAGE 160
SAM D21 Family PM – Power Manager 16.8.8 APBA Mask Name: Offset: Reset: Property: Bit APBAMASK 0x18 0x0000007F Write-Protected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset EIC RTC WDT GCLK SYSCTRL PM PAC0 R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 Bit 6 – EIC EIC APB Clock Enable Value 0 1 Description The APBA clock for the EIC is stopped.
PAGE 161
SAM D21 Family PM – Power Manager Bit 2 – SYSCTRL SYSCTRL APB Clock Enable Value 0 1 Description The APBA clock for the SYSCTRL is stopped. The APBA clock for the SYSCTRL is enabled. Bit 1 – PM PM APB Clock Enable Value 0 1 Description The APBA clock for the PM is stopped. The APBA clock for the PM is enabled. Bit 0 – PAC0 PAC0 APB Clock Enable Value 0 1 Description The APBA clock for the PAC0 is stopped. The APBA clock for the PAC0 is enabled. © 2018 Microchip Technology Inc.
PAGE 162
SAM D21 Family PM – Power Manager 16.8.9 APBB Mask Name: Offset: Reset: Property: Bit APBBMASK 0x1C 0x0000007F Write-Protected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USB DMAC PORT NVMCTRL DSU PAC1 R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 5 – USB USB APB Clock Enable Value 0 1 Description The APBB clock for the USB is stopped.
PAGE 163
SAM D21 Family PM – Power Manager Bit 1 – DSU DSU APB Clock Enable Value 0 1 Description The APBB clock for the DSU is stopped. The APBB clock for the DSU is enabled. Bit 0 – PAC1 PAC1 APB Clock Enable Value 0 1 Description The APBB clock for the PAC1 is stopped. The APBB clock for the PAC1 is enabled. © 2018 Microchip Technology Inc.
PAGE 164
SAM D21 Family PM – Power Manager 16.8.
PAGE 165
SAM D21 Family PM – Power Manager Bit 18 – DAC DAC APB Clock Enable Value 0 1 Description The APBC clock for the DAC is stopped The APBC clock for the DAC is enabled Bit 17 – AC AC APB Clock Enable Value 0 1 Description The APBC clock for the AC is stopped The APBC clock for the AC is enabled Bit 16 – ADC ADC APB Clock Enable Value 0 1 Description The APBC clock for the ADC is stopped The APBC clock for the ADC is enabled Bit 15 – TC7 TC7 APB Clock Enable Value 0 1 Description The APBC clock for the
PAGE 166
SAM D21 Family PM – Power Manager Bit 9 – TCC1 TCC1 APB Clock Enable Value 0 1 Description The APBC clock for the TCC1 is stopped The APBC clock for the TCC1 is enabled Bit 8 – TCC0 TCC0 APB Clock Enable Value 0 1 Description The APBC clock for the TCC0 is stopped The APBC clock for the TCC0 is enabled Bit 7 – SERCOM5 SERCOM5 APB Clock Enable Value 0 1 Description The APBC clock for the SERCOM5 is stopped The APBC clock for the SERCOM5 is enabled Bit 6 – SERCOM4 SERCOM4 APB Clock Enable Value 0 1 Des
PAGE 167
SAM D21 Family PM – Power Manager Bit 0 – PAC2 PAC2 APB Clock Enable Value 0 1 Description The APBC clock for the PAC2 is stopped The APBC clock for the PAC2 is enabled © 2018 Microchip Technology Inc.
PAGE 168
SAM D21 Family PM – Power Manager 16.8.11 Interrupt Enable Clear Name: Offset: Reset: Property: Bit 7 INTENCLR 0x34 0x00 Write-Protected 6 5 4 3 2 1 0 CKRDY Access R/W Reset 0 Bit 0 – CKRDY Clock Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the Clock Ready Interrupt Enable bit and the corresponding interrupt request. Value 0 1 Description The Clock Ready interrupt is disabled.
PAGE 169
SAM D21 Family PM – Power Manager 16.8.12 Interrupt Enable Set Name: Offset: Reset: Property: Bit 7 INTENSET 0x35 0x00 Write-Protected 6 5 4 3 2 1 0 CKRDY Access R/W Reset 0 Bit 0 – CKRDY Clock Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the Clock Ready Interrupt Enable bit and enable the Clock Ready interrupt. Value 0 1 Description The Clock Ready interrupt is disabled. The Clock Ready interrupt is enabled.
PAGE 170
SAM D21 Family PM – Power Manager 16.8.13 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 INTFLAG 0x36 0x00 - 6 5 4 3 2 1 0 CKRDY Access R/W Reset 0 Bit 0 – CKRDY Clock Ready This flag is cleared by writing a one to the flag. This flag is set when the synchronous CPU and APBx clocks have frequencies as indicated in the CPUSEL and APBxSEL registers, and will generate an interrupt if INTENCLR/SET.CKRDY is one. Writing a zero to this bit has no effect.
PAGE 171
SAM D21 Family PM – Power Manager 16.8.14 Reset Cause Name: Offset: Reset: Property: Bit 7 RCAUSE 0x38 0x01 - 6 5 4 2 1 0 SYST WDT EXT 3 BOD33 BOD12 POR Access R R R R R R Reset 0 0 0 0 0 1 Bit 6 – SYST System Reset Request This bit is set if a system reset request has been performed. Refer to the Cortex processor documentation for more details. Bit 5 – WDT Watchdog Reset This flag is set if a Watchdog Timer reset occurs.
PAGE 172
SAM D21 Family SYSCTRL – System Controller 17. SYSCTRL – System Controller 17.1 Overview The System Controller (SYSCTRL) provides a user interface to the clock sources, brown out detectors, on-chip voltage regulator and voltage reference of the device. Through the interface registers, it is possible to enable, disable, calibrate and monitor the SYSCTRL subperipherals. All sub-peripheral statuses are collected in the Power and Clocks Status register (PCLKSR).
PAGE 173
SAM D21 Family SYSCTRL – System Controller • • • • • Fractional Digital Phase Locked Loop (FDPLL96M) – 48MHz to 96MHz output clock frequency – 32KHz to 2MHz input reference clock frequency range – Three possible sources for the reference clock – Adjustable proportional integral controller – Fractional part used to achieve 1/16th of reference clock step 3.
PAGE 174
SAM D21 Family SYSCTRL – System Controller 17.3 Block Diagram Figure 17-1. SYSCTRL Block Diagram SYSCTRL XOSC XOSC32K OSC32K OSCILLATORS CONTROL OSCULP32K OSC8M DFLL48M FDPLL96M POWER MONITOR CONTROL VOLTAGE REFERENCE CONTROL BOD33 VOLTAGE REFERENCE SYSTEM STATUS (PCLKSR register) INTERRUPTS GENERATOR 17.
PAGE 175
SAM D21 Family SYSCTRL – System Controller 17.5.1 I/O Lines I/O lines are configured by SYSCTRL when either XOSC or XOSC32K are enabled, and need no user configuration. 17.5.2 Power Management The SYSCTRL can continue to operate in any sleep mode where the selected source clock is running. The SYSCTRL interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes. Refer to PM – Power Manager on the different sleep modes.
PAGE 176
SAM D21 Family SYSCTRL – System Controller Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger. 17.5.7 Analog Connections When used, the 32.768kHz crystal must be connected between the XIN32 and XOUT32 pins, and the 0.4-32MHz crystal must be connected between the XIN and XOUT pins, along with any required load capacitors.
PAGE 177
SAM D21 Family SYSCTRL – System Controller To force the oscillator to run in Standby mode, the RUNSTDBY bit must be written to one. The oscillator will then run in Standby mode when requested by a peripheral (ONDEMAND is one). To force an oscillator to always run in Standby mode, and not only when requested by a peripheral, the ONDEMAND bit must be written to zero and RUNSTDBY must be written to one.
PAGE 178
SAM D21 Family SYSCTRL – System Controller ...........continued XOSC.RUNSTDBY XOSC.ONDEMAND XOSC.ENABLE Sleep Behavior 0 0 1 Always run in IDLE sleep modes. Disabled in STANDBY sleep mode. 0 1 1 Only run in IDLE sleep modes if requested by a peripheral. Disabled in STANDBY sleep mode. 1 0 1 Always run in IDLE and STANDBY sleep modes. 1 1 1 Only run in IDLE or STANDBY sleep modes if requested by a peripheral.
PAGE 179
SAM D21 Family SYSCTRL – System Controller XOSC32K.ENABLE bit while writing to other bits may result in unpredictable behavior. The oscillator remains enabled in all sleep modes if it has been enabled beforehand. The start-up time of the 32kHz External Crystal Oscillator is selected by writing to the Oscillator Start-Up Time bit group (XOSC32K.STARTUP) in the in the 32kHz External Crystal Oscillator Control register.
PAGE 180
SAM D21 Family SYSCTRL – System Controller The OSCULP32K is enabled by default after a power-on reset (POR) and will always run except during POR. The OSCULP32K has a 32.768kHz output and a 1.024kHz output that are always running. The frequency of the OSCULP32K oscillator is controlled by the value in the 32kHz Ultra Low Power Internal Oscillator Calibration bits (OSCULP32K.CALIB) in the 32kHz Ultra Low Power Internal Oscillator Control register. OSCULP32K.
PAGE 181
SAM D21 Family SYSCTRL – System Controller 17.6.7.1 Basic Operation 17.6.7.1.1 Open-Loop Operation After any reset, the open-loop mode is selected. When operating in open-loop mode, the output frequency of the DFLL48M will be determined by the values written to the DFLL Coarse Value bit group and the DFLL Fine Value bit group (DFLLVAL.COARSE and DFLLVAL.FINE) in the DFLL Value register. Using "DFLL48M COARSE CAL" value from NVM Software Calibration Area Mapping in DFLL.
PAGE 182
SAM D21 Family SYSCTRL – System Controller 3. Start DFLL close loop This procedure will reduce DFLL Lock time to DFLL Fine lock time. Related Links 15. GCLK - Generic Clock Controller 10.3.2 NVM Software Calibration Area Mapping 17.6.7.1.3 Frequency Locking The locking of the frequency in closed-loop mode is divided into two stages. In the first, coarse stage, the control logic quickly finds the correct value for DFLLVAL.COARSE and sets the output frequency to a value close to the correct frequency.
PAGE 183
SAM D21 Family SYSCTRL – System Controller interrupt is generated on a zero-to-one transition on PCLKSR.DFLLRCS if the DFLL Reference Clock Stopped bit (INTENSET.DFLLRCS) in the Interrupt Enable Set register is set. 17.6.7.2 Additional Features 17.6.7.2.1 Dealing with Delay in the DFLL in Closed-Loop Mode The time from selecting a new CLK_DFLL48M frequency until this frequency is output by the DFLL48M can be up to several microseconds. If the value in DFLLMUL.
PAGE 184
SAM D21 Family SYSCTRL – System Controller • 17.6.8 DFLL48M might lock at a frequency that is lower than the targeted frequency. It is recommended to use a reference clock frequency of 32kHz or lower to avoid this issue for low target frequencies. The accuracy of the reference clock. FDPLL96M – Fractional Digital Phase-Locked Loop Controller (DFLL96M) 17.6.8.1 Overview The FDPLL96M controller allows flexible interface to the core digital function of the Digital Phase Locked Loop (DPLL).
PAGE 185
SAM D21 Family SYSCTRL – System Controller 17.6.8.3 Principle of Operation The task of the FDPLL96M is to maintain coherence between the input reference clock signal (CLK_FDPLL96M_REF) and the respective output frequency CK via phase comparison. The FDPLL96M supports three independent sources of clocks; XOSC32K, XOSC and GCLK_DPLL. When the FDPLL96M is enabled, the relationship between the reference clock (CLK_FDPLL96M_REF) frequency and the output clock (CLK_FDPLL96M) frequency is defined below.
PAGE 186
SAM D21 Family SYSCTRL – System Controller Table 17-5. CLK_FDPLL96M behavior after First Edge detection. LBYPASS CLK_FDPLL96M Behavior 0 Normal Mode: the CLK_FDPLL96M is turned off when lock signal is low. 1 Lock Bypass Mode: the CLK_FDPLL96M is always running, lock is irrelevant. Figure 17-3. CK and CLK_FDPLL96M Off Mode to Running Mode CKRx ENABLE CK CLK_FDPLL96M LOCK Figure 17-4.
PAGE 187
SAM D21 Family SYSCTRL – System Controller 17.6.8.5 Reference Clock Switching When a software operation requires reference clock switching, the normal operation is to disable the FDPLL96M, modify the DPLLCTRLB.REFCLK to select the desired reference source and activate the FDPLL96M again. 17.6.8.
PAGE 188
SAM D21 Family SYSCTRL – System Controller 17.6.9.2 Continuous Mode When the BOD33 Mode bit (BOD33.MODE) in the BOD33 register is written to zero and the BOD33 is enabled, the BOD33 operates in continuous mode. In this mode, the BOD33 is continuously monitoring the VDDANA supply voltage. Continuous mode is the default mode for BOD33. 17.6.9.3 Sampling Mode The sampling mode is a low-power mode where the BOD33 or BOD12 is being repeatedly enabled on a sampling clock’s ticks.
PAGE 189
SAM D21 Family SYSCTRL – System Controller level. Writing a one to the BOD12 Hysteresis bit (BOD12.HYST) in the BOD12 register will add hysteresis to the BOD12 threshold level. 17.6.10 Voltage Reference System Operation The Voltage Reference System (VREF) consists of a Bandgap Reference Voltage Generator and a temperature sensor. The Bandgap Reference Voltage Generator is factory-calibrated under typical voltage and temperature conditions. At reset, the VREF.
PAGE 190
SAM D21 Family SYSCTRL – System Controller • • • • • • • • • • • • • • DFLLRDY - DFLL48M Ready: A “0-to-1” transition on the PCLKSR.DFLLRDY bit is detected DFLLOOB - DFLL48M Out Of Boundaries: A “0-to-1” transition on the PCLKSR.DFLLOOB bit is detected DFLLLOCKF - DFLL48M Fine Lock: A “0-to-1” transition on the PCLKSR.DFLLLOCKF bit is detected DFLLLOCKC - DFLL48M Coarse Lock: A “0-to-1” transition on the PCLKSR.
PAGE 191
SAM D21 Family SYSCTRL – System Controller while DFLLRDY is zero will be ignored. An interrupt is generated on a zero-to-one transition of DFLLRDY if the DFLLRDY bit (INTENSET.DFLLDY) in the Interrupt Enable Set register is set. In order to read from any of the DFLL48M configuration registers, the user must request a read synchronization by writing a one to DFLLSYNC.READREQ. The registers can be read only when PCLKSR.DFLLRDY is set. If DFLLSYNC.
PAGE 192
SAM D21 Family SYSCTRL – System Controller 17.7 Offset 0x00 Register Summary Name INTENCLR Bit Pos.
PAGE 193
SAM D21 Family SYSCTRL – System Controller ...........continued Offset Name Bit Pos. 0x26 ... Reserved 0x27 7:0 0x28 DFLLVAL 0x2C DFLLMUL 0x30 DFLLSYNC FINE[7:0] 15:8 COARSE[5:0] FINE[9:8] 23:16 DIFF[7:0] 31:24 DIFF[15:8] 7:0 MUL[7:0] 15:8 MUL[15:8] 23:16 FSTEP[7:0] 31:24 7:0 CSTEP[5:0] FSTEP[9:8] READREQ 0x31 ... Reserved 0x33 7:0 0x34 BOD33 RUNSTDBY 15:8 ACTION[1:0] HYST ENABLE PSEL[3:0] CEN 23:16 MODE LEVEL[5:0] 31:24 0x38 ...
PAGE 194
SAM D21 Family SYSCTRL – System Controller 17.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.
PAGE 195
SAM D21 Family SYSCTRL – System Controller 17.8.
PAGE 196
SAM D21 Family SYSCTRL – System Controller Bit 15 – DPLLLCKR DPLL Lock Rise Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the DPLL Lock Rise Interrupt Enable bit, which disables the DPLL Lock Rise interrupt. Value 0 1 Description The DPLL Lock Rise interrupt is disabled. The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Rise Interrupt flag is set.
PAGE 197
SAM D21 Family SYSCTRL – System Controller Bit 7 – DFLLLCKC DFLL Lock Coarse Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the DFLL Lock Coarse Interrupt Enable bit, which disables the DFLL Lock Coarse interrupt. Value 0 1 Description The DFLL Lock Coarse interrupt is disabled. The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Coarse Interrupt flag is set.
PAGE 198
SAM D21 Family SYSCTRL – System Controller Bit 2 – OSC32KRDY OSC32K Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the OSC32K Ready Interrupt Enable bit, which disables the OSC32K Ready interrupt. Value 0 1 Description The OSC32K Ready interrupt is disabled. The OSC32K Ready interrupt is enabled, and an interrupt request will be generated when the OSC32K Ready Interrupt flag is set.
PAGE 199
SAM D21 Family SYSCTRL – System Controller 17.8.
PAGE 200
SAM D21 Family SYSCTRL – System Controller Bit 15 – DPLLLCKR DPLL Lock Rise Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the DPLL Lock Rise Interrupt Enable bit, which enables the DPLL Lock Rise interrupt. Value 0 1 Description The DPLL Lock Rise interrupt is disabled. The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Rise Interrupt flag is set.
PAGE 201
SAM D21 Family SYSCTRL – System Controller Bit 7 – DFLLLCKC DFLL Lock Coarse Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the DFLL Lock Coarse Interrupt Enable bit, which enables the DFLL Lock Coarse interrupt. Value 0 1 Description The DFLL Lock Coarse interrupt is disabled. The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Coarse Interrupt flag is set.
PAGE 202
SAM D21 Family SYSCTRL – System Controller Bit 2 – OSC32KRDY OSC32K Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the OSC32K Ready Interrupt Enable bit, which enables the OSC32K Ready interrupt. Value 0 1 Description The OSC32K Ready interrupt is disabled. The OSC32K Ready interrupt is enabled, and an interrupt request will be generated when the OSC32K Ready Interrupt flag is set.
PAGE 203
SAM D21 Family SYSCTRL – System Controller 17.8.3 Interrupt Flag Status and Clear Name: Offset: Reset: Property: INTFLAG 0x08 0x00000000 - Note: Depending on the fuse settings, various bits of the INTFLAG register can be set to one at startup. Therefore the user should clear those bits before using the corresponding interrupts.
PAGE 204
SAM D21 Family SYSCTRL – System Controller This flag is set on a zero-to-one transition of the DPLL Lock Rise bit in the Status register (PCLKSR.DPLLLCKR) and will generate an interrupt request if INTENSET.DPLLLCKR is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the DPLL Lock Rise interrupt flag. Bit 11 – B33SRDY BOD33 Synchronization Ready This flag is cleared by writing a one to it.
PAGE 205
SAM D21 Family SYSCTRL – System Controller This flag is set on a zero-to-one transition of the DFLL Lock Fine bit in the Status register (PCLKSR.DFLLLCKF) and will generate an interrupt request if INTENSET.DFLLLCKF is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the DFLL Lock Fine interrupt flag. Bit 5 – DFLLOOB DFLL Out Of Bounds This flag is cleared by writing a one to it.
PAGE 206
SAM D21 Family SYSCTRL – System Controller This flag is set on a zero-to-one transition of the XOSC Ready bit in the Status register (PCLKSR.XOSCRDY) and will generate an interrupt request if INTENSET.XOSCRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the XOSC Ready interrupt flag. © 2018 Microchip Technology Inc.
PAGE 207
SAM D21 Family SYSCTRL – System Controller 17.8.
PAGE 208
SAM D21 Family SYSCTRL – System Controller Bit 10 – BOD33DET BOD33 Detection Value 0 1 Description No BOD33 detection. BOD33 has detected that the I/O power supply is going below the BOD33 reference value. Bit 9 – BOD33RDY BOD33 Ready Value 0 1 Description BOD33 is not ready. BOD33 is ready. Bit 8 – DFLLRCS DFLL Reference Clock Stopped Value 0 1 Description DFLL reference clock is running. DFLL reference clock has stopped.
PAGE 209
SAM D21 Family SYSCTRL – System Controller Value 0 1 Description OSC32K is not ready. OSC32K is stable and ready to be used as a clock source. Bit 1 – XOSC32KRDY XOSC32K Ready Value 0 1 Description XOSC32K is not ready. XOSC32K is stable and ready to be used as a clock source. Bit 0 – XOSCRDY XOSC Ready Value 0 1 Description XOSC is not ready. XOSC is stable and ready to be used as a clock source. © 2018 Microchip Technology Inc.
PAGE 210
SAM D21 Family SYSCTRL – System Controller 17.8.
PAGE 211
SAM D21 Family SYSCTRL – System Controller Note: 1. Number of cycles for the start-up counter 2. Number of cycles for the synchronization delay, before PCLKSR.XOSCRDY is set. 3. Actual start-up time is n OSCULP32K cycles + 3 XOSC cycles, but given the time neglects the 3 XOSC cycles. Bit 11 – AMPGC Automatic Amplitude Gain Control This bit must be set only after the XOSC has settled, indicated by the XOSC Ready flag in the PCLKSR register (PCLKSR.XOSCRDY).
PAGE 212
SAM D21 Family SYSCTRL – System Controller Value 0 1 Description The oscillator is disabled in standby sleep mode. The oscillator is not stopped in standby sleep mode. If XOSC.ONDEMAND is one, the clock source will be running when a peripheral is requesting the clock. If XOSC.ONDEMAND is zero, the clock source will always be running in standby sleep mode.
PAGE 213
SAM D21 Family SYSCTRL – System Controller 17.8.
PAGE 214
SAM D21 Family SYSCTRL – System Controller 3. Start-up time is n OSCULP32K cycles + 3 XOSC32K cycles. Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock requests. In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will only be running when requested by a peripheral.
PAGE 215
SAM D21 Family SYSCTRL – System Controller Value 0 1 Description The oscillator is disabled. The oscillator is enabled. © 2018 Microchip Technology Inc.
PAGE 216
SAM D21 Family SYSCTRL – System Controller 17.8.
PAGE 217
SAM D21 Family SYSCTRL – System Controller Table 17-7. Start-Up Time for 32kHz Internal Oscillator STARTUP[2:0] Number of OSC32K clock cycles Approximate Equivalent Time (OSCULP= 32 kHz)(1)(2)(3) 0x0 3 92μs 0x1 4 122μs 0x2 6 183μs 0x3 10 305μs 0x4 18 549μs 0x5 34 1038μs 0x6 66 2014μs 0x7 130 3967μs Notes: 1. Number of cycles for the start-up counter. 2. Number of cycles for the synchronization delay, before PCLKSR.OSC32KRDY is set. 3.
PAGE 218
SAM D21 Family SYSCTRL – System Controller Value 0 1 0 1 Description The 32kHz output is disabled. The 32kHz output is enabled. The oscillator is disabled. The oscillator is enabled. Bit 1 – ENABLE Oscillator Enable Value 0 1 Description The oscillator is disabled. The oscillator is enabled. © 2018 Microchip Technology Inc.
PAGE 219
SAM D21 Family SYSCTRL – System Controller 17.8.8 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control Name: Offset: Reset: Property: Bit 7 OSCULP32K 0x1C 0xXX Write-Protected 6 5 4 3 WRTLOCK Access Reset 2 1 0 CALIB[4:0] R/W R/W R/W R/W R/W R/W 0 x x x x x Bit 7 – WRTLOCK Write Lock This bit locks the OSCULP32K register for future writes to fix the OSCULP32K configuration. Value 0 1 Description The OSCULP32K configuration is not locked.
PAGE 220
SAM D21 Family SYSCTRL – System Controller 17.8.
PAGE 221
SAM D21 Family SYSCTRL – System Controller PRESC[1:0] Description 0x0 1 0x1 2 0x2 4 0x3 8 Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock requests. In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will only be running when requested by a peripheral.
PAGE 222
SAM D21 Family SYSCTRL – System Controller 17.8.
PAGE 223
SAM D21 Family SYSCTRL – System Controller If On Demand is disabled the oscillator will always be running when enabled. In standby sleep mode, the On Demand operation is still active if the DFLLCTRL.RUNSTDBY bit is one. If DFLLCTRL.RUNSTDBY is zero, the oscillator is disabled. Value 0 1 Description The oscillator is always on, if enabled. The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source.
PAGE 224
SAM D21 Family SYSCTRL – System Controller 17.8.
PAGE 225
SAM D21 Family SYSCTRL – System Controller 17.8.
PAGE 226
SAM D21 Family SYSCTRL – System Controller 17.8.13 DFLL48M Synchronization Name: Offset: Reset: Property: Bit 7 DFLLSYNC 0x30 0x00 Write-Protected 6 5 4 3 2 1 0 READREQ Access W Reset 0 Bit 7 – READREQ Read Request To be able to read the current value of DFLLVAL in closed-loop mode, this bit should be written to one. The updated value is available in DFLLVAL when PCLKSR.DFLLRDY is set. © 2018 Microchip Technology Inc.
PAGE 227
SAM D21 Family SYSCTRL – System Controller 17.8.14 3.
PAGE 228
SAM D21 Family SYSCTRL – System Controller ...........
PAGE 229
SAM D21 Family SYSCTRL – System Controller ...........continued ACTION[1:0] Name 0x3 Description Reserved Bit 2 – HYST Hysteresis This bit indicates whether hysteresis is enabled for the BOD33 threshold voltage: This bit is loaded from Flash User Row at start-up. Refer to NVM User Row Mapping for more details. Value 0 1 Description No hysteresis. Hysteresis enabled. Bit 1 – ENABLE Enable This bit is loaded from Flash User Row at startup. Refer to NVM User Row Mapping for more details.
PAGE 230
SAM D21 Family SYSCTRL – System Controller 17.8.15 Voltage Regulator System (VREG) Control Name: Offset: Reset: Property: Bit 15 VREG 0x3C 0x0X00 Write-Protected 14 13 12 11 10 9 8 4 3 2 1 0 FORCELDO Access R/W Reset Bit 0 7 6 5 RUNSTDBY Access R/W Reset 0 Bit 13 – FORCELDO Force LDO Voltage Regulator Value 0 1 Description The voltage regulator is in low power and low drive configuration in standby sleep mode.
PAGE 231
SAM D21 Family SYSCTRL – System Controller 17.8.
PAGE 232
SAM D21 Family SYSCTRL – System Controller 17.8.17 DPLL Control A Name: Offset: Reset: Property: Bit Access Reset DPLLCTRLA 0x44 0x80 Write-Protected 7 6 ONDEMAND RUNSTDBY 5 4 3 2 ENABLE 1 R/W R/W R/W 1 0 0 0 Bit 7 – ONDEMAND On Demand Clock Activation Value 0 1 Description The DPLL is always on when enabled. The DPLL is activated only when a peripheral request the DPLL as a source clock. The DPLLCTRLA.
PAGE 233
SAM D21 Family SYSCTRL – System Controller 17.8.
PAGE 234
SAM D21 Family SYSCTRL – System Controller 17.8.
PAGE 235
SAM D21 Family SYSCTRL – System Controller ...........continued LTIME[2:0] Name Description 0x7 11MS Time-out if no lock within 11 ms Bits 5:4 – REFCLK[1:0] Reference Clock Selection These bits select the CLK_FDPLL96M_REF source. REFCLK[1:0] Name Description 0x0 XOSC32 XOSC32 clock reference 0x1 XOSC XOSC clock reference 0x2 GCLK_DPLL GCLK_DPLL clock reference 0x3 Reserved Bit 3 – WUF Wake Up Fast Value 0 1 Description DPLL CK output is gated until complete startup time and lock time.
PAGE 236
SAM D21 Family SYSCTRL – System Controller 17.8.20 DPLL Status Name: Offset: Reset: Property: Bit 7 DPLLSTATUS 0x50 0x00 - 6 5 4 3 2 1 0 DIV ENABLE CLKRDY LOCK Access R R R R Reset 0 0 0 0 Bit 3 – DIV Divider Enable Value 0 1 Description The reference clock divider is disabled. The reference clock divider is enabled. Bit 2 – ENABLE DPLL Enable Value 0 1 Description The DPLL is disabled. The DPLL is enabled.
PAGE 237
SAM D21 Family WDT – Watchdog Timer 18. 18.1 WDT – Watchdog Timer Overview The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover from error situations such as runaway or deadlocked code. The WDT is configured to a predefined time-out period, and is constantly running when enabled. If the WDT is not cleared within the time-out period, it will issue a system reset.
PAGE 238
SAM D21 Family WDT – Watchdog Timer 18.3 Block Diagram Figure 18-1. WDT Block Diagram 0xA5 0 CLEAR GCLK_WDT COUNT PER/WINDOW/EWOFFSET Early Warning Interrupt Reset 18.4 Signal Description Not applicable. 18.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 18.5.1 I/O Lines Not applicable. 18.5.2 Power Management The WDT can continue to operate in any sleep mode where the selected source clock is running.
PAGE 239
SAM D21 Family WDT – Watchdog Timer vary from device to device. This variation must be kept in mind when designing software that uses the WDT to ensure that the time-out periods used are valid for all devices. For more information on ULP oscillator accuracy, consult the Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics. GCLK_WDT can also be clocked from other sources if a more accurate clock is needed, but at the cost of higher power consumption. Related Links 16.
PAGE 240
SAM D21 Family WDT – Watchdog Timer constantly running timer that is configured to a predefined time-out period. Before the end of the time-out period, the WDT should be set back, or else, a system Reset is issued. The WDT has two modes of operation, Normal mode and Window mode. Both modes offer the option of Early Warning interrupt generation. The description for each of the basic modes is given below.
PAGE 241
SAM D21 Family WDT – Watchdog Timer Window Mode • Defining Time-Out Period bits in the Configuration register (CONFIG.PER). • Defining Window Mode Time-Out Period bits in the Configuration register (CONFIG.WINDOW). • Setting Window Enable bit in the Control register (CTRL.WEN). Window Mode with Early Warning interrupt • Defining Time-Out Period bits in the Configuration register (CONFIG.PER). • Defining Window Mode Time-Out Period bits in the Configuration register (CONFIG.WINDOW).
PAGE 242
SAM D21 Family WDT – Watchdog Timer (INTENCLR.EW). If the Early Warning Interrupt is enabled, an interrupt is generated prior to a WDT timeout condition. In Normal mode, the Early Warning Offset bits in the Early Warning Interrupt Control register, EWCTRL.EWOFFSET, define the time when the early warning interrupt occurs. The Normal mode operation is illustrated in the figure Normal-Mode Operation. Figure 18-2.
PAGE 243
SAM D21 Family WDT – Watchdog Timer The Configuration (CONFIG) and Early Warning Control (EWCTRL) registers are read-only registers while the CTRL.ALWAYSON bit is set. Thus, the time period configuration bits (CONFIG.PER, CONFIG.WINDOW, EWCTRL.EWOFFSET) of the WDT cannot be changed. Enabling or disabling Window mode operation by writing the Window Enable bit (CTRLA.WEN) is allowed while in Always-On mode, but note that CONFIG.PER cannot be changed. The CTRL.
PAGE 244
SAM D21 Family WDT – Watchdog Timer period, the watchdog time-out system reset is generated prior to the Early Warning interrupt. Thus, the Early Warning interrupt will never be generated. In window mode, the Early Warning interrupt is generated at the start of the open window period. In a typical application where the system is in sleep mode, it can use this interrupt to wake up and clear the Watchdog Timer, after which the system can perform other tasks or return to sleep mode. 18.6.
PAGE 245
SAM D21 Family WDT – Watchdog Timer 18.7 Register Summary Offset Name Bit Pos. 0x00 CTRL 7:0 0x01 CONFIG 7:0 0x02 EWCTRL 7:0 ALWAYSON WEN WINDOW[3:0] ENABLE PER[3:0] EWOFFSET[3:0] 0x03 Reserved 0x04 INTENCLR 7:0 EW 0x05 INTENSET 7:0 EW 0x06 INTFLAG 7:0 0x07 STATUS 7:0 0x08 CLEAR 7:0 18.8 EW SYNCBUSY CLEAR[7:0] Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported.
PAGE 246
SAM D21 Family WDT – Watchdog Timer 18.8.1 Control Name: Offset: Reset: Property: Bit Access Reset CTRL 0x0 N/A - Loaded from NVM User Row at start-up Write-Protected, Enable-Protected, Write-Synchronized 2 1 ALWAYSON 7 6 5 4 3 WEN ENABLE R/W R/W R/W x x x 0 Bit 7 – ALWAYSON Always-On This bit allows the WDT to run continuously. After being written to one, this bit cannot be written to zero, and the WDT will remain enabled until a power-on reset is received.
PAGE 248
SAM D21 Family WDT – Watchdog Timer 18.8.2 Configuration Name: Offset: Reset: Property: Bit 7 CONFIG 0x1 N/A - Loaded from NVM User Row at startup Write-Protected, Enable-Protected, Write-Synchronized 6 5 4 3 2 WINDOW[3:0] Access Reset 1 0 PER[3:0] R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 7:4 – WINDOW[3:0] Window Mode Time-Out Period In window mode, these bits determine the watchdog closed window period as a number of oscillator cycles.
PAGE 249
SAM D21 Family WDT – Watchdog Timer Value 0x9 0xA 0xB 0xC-0xF Description 4096 clock cycles 8192 clock cycles 16384 clock cycles Reserved Related Links 10.3.1 NVM User Row Mapping © 2018 Microchip Technology Inc.
PAGE 250
SAM D21 Family WDT – Watchdog Timer 18.8.3 Early Warning Interrupt Control Name: Offset: Reset: Property: Bit 7 EWCTRL 0x2 N/A - Loaded from NVM User Row at start-up Write-Protected, Enable-Protected 6 5 4 3 2 1 0 EWOFFSET[3:0] Access Reset R/W R/W R/W R/W x x x x Bits 3:0 – EWOFFSET[3:0] Early Warning Interrupt Time Offset These bits determine the number of GCLK_WDT clocks in the offset from the start of the watchdog timeout period to when the Early Warning interrupt is generated.
PAGE 251
SAM D21 Family WDT – Watchdog Timer 18.8.4 Interrupt Enable Clear Name: Offset: Reset: Property: Bit 7 INTENCLR 0x4 0x00 Write-Protected 6 5 4 3 2 1 0 EW Access R/W Reset 0 Bit 0 – EW Early Warning Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit disables the Early Warning interrupt. Value 0 1 Description The Early Warning interrupt is disabled. The Early Warning interrupt is enabled. © 2018 Microchip Technology Inc.
PAGE 252
SAM D21 Family WDT – Watchdog Timer 18.8.5 Interrupt Enable Set Name: Offset: Reset: Property: Bit 7 INTENSET 0x5 0x00 Write-Protected 6 5 4 3 2 1 0 EW Access R/W Reset 0 Bit 0 – EW Early Warning Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit enables the Early Warning interrupt. Value 0 1 Description The Early Warning interrupt is disabled. The Early Warning interrupt is enabled. © 2018 Microchip Technology Inc.
PAGE 253
SAM D21 Family WDT – Watchdog Timer 18.8.6 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 INTFLAG 0x6 0x00 – 6 5 4 3 2 1 0 EW Access R/W Reset 0 Bit 0 – EW Early Warning This flag is set when an Early Warning interrupt occurs, as defined by the EWOFFSET bit group in EWCTRL. Writing a zero to this bit has no effect. Writing a one to this bit clears the Early Warning interrupt flag. © 2018 Microchip Technology Inc.
PAGE 254
SAM D21 Family WDT – Watchdog Timer 18.8.7 Status Name: Offset: Reset: Property: Bit 7 STATUS 0x7 0x00 – 6 5 4 3 2 1 0 SYNCBUSY Access R Reset 0 Bit 7 – SYNCBUSY Synchronization Busy This bit is cleared when the synchronization of registers between clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. © 2018 Microchip Technology Inc.
PAGE 255
SAM D21 Family WDT – Watchdog Timer 18.8.8 Clear Name: Offset: Reset: Property: Bit 7 CLEAR 0x8 0x00 Write-Protected, Write-Synchronized 6 5 4 3 2 1 0 CLEAR[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – CLEAR[7:0] Watchdog Clear Writing 0xA5 to this register will clear the Watchdog Timer and the watchdog time-out period is restarted. Writing any other value will issue an immediate system reset. © 2018 Microchip Technology Inc.
PAGE 256
SAM D21 Family RTC – Real-Time Counter 19. RTC – Real-Time Counter 19.1 Overview The Real-Time Counter (RTC) is a 32-bit counter with a 10-bit programmable prescaler that typically runs continuously to keep track of time. The RTC can wake up the device from sleep modes using the alarm/ compare wake up, periodic wake up, or overflow wake up mechanisms The RTC is typically clocked by the 1.024kHz output from the 32.
PAGE 257
SAM D21 Family RTC – Real-Time Counter 19.3 Block Diagram Figure 19-1. RTC Block Diagram (Mode 0 — 32-Bit Counter) 0 MATCHCLR GCLK_RTC 10-bit Prescaler CLK_RTC_CNT Overflow COUNT 32 = Periodic Events Compare n 32 COMPn Figure 19-2. RTC Block Diagram (Mode 1 — 16-Bit Counter) 0 GCLK_RTC 10-bit Prescaler CLK_RTC_CNT COUNT = 16 Overflow 16 Periodic Events PER = Compare n 16 COMPn Figure 19-3.
PAGE 258
SAM D21 Family RTC – Real-Time Counter 19.5.1 I/O Lines Not applicable. 19.5.2 Power Management The RTC will continue to operate in any sleep mode where the selected source clock is running. The RTC interrupts can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations in the system without exiting sleep modes. Refer to the Power Manager for details on the different sleep modes.
PAGE 259
SAM D21 Family RTC – Real-Time Counter 19.5.8 Register Access Protection Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following: • • • • Interrupt Flag Status and Clear register (INTFLAG) Read Request register (READREQ) Status register (STATUS) Debug register (DBGCTRL) Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description.
PAGE 260
SAM D21 Family RTC – Real-Time Counter Enable-protection is denoted by the "Enable-Protected" property in the register description. Before the RTC is enabled, it must be configured, as outlined by the following steps: 1. RTC operation mode must be selected by writing the Operating Mode bit group in the Control register (CTRL.MODE) 2. Clock representation must be selected by writing the Clock Representation bit in the Control register (CTRL.CLKREP) 3.
PAGE 261
SAM D21 Family RTC – Real-Time Counter 19.6.3.2 16-Bit Counter (Mode 1) When the RTC Operating Mode bits in the Control register (CTRL.MODE) are 1, the counter operates in 16-bit Counter mode as shown in Figure 19-2. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. In 16-bit Counter mode, the 16-bit Period register (PER) holds the maximum value of the counter. The counter will increment until it reaches the PER value, and then wrap to 0x0000.
PAGE 262
SAM D21 Family RTC – Real-Time Counter Periodic Events). Note that when CTRL.MATCHCLR is '1', INTFLAG.ALARM0 and INTFLAG.OVF will both be set simultaneously on an alarm match with ALARM0. 19.6.4 DMA Operation Not applicable. 19.6.5 Interrupts The RTC has the following interrupt sources which are asynchronous interrupts and can wake-up the device from any sleep mode.: • • • • Overflow (INTFLAG.OVF): Indicates that the counter has reached its top value and wrapped to zero. Compare n (INTFLAG.
PAGE 263
SAM D21 Family RTC – Real-Time Counter 19.6.7 Sleep Mode Operation The RTC will continue to operate in any sleep mode where the source clock is active. The RTC interrupts can be used to wake up the device from a sleep mode. RTC events can trigger other operations in the system without exiting the sleep mode. An interrupt request will be generated after the wake-up if the Interrupt Controller is configured accordingly. Otherwise the CPU will wake up directly, without triggering any interrupt.
PAGE 264
SAM D21 Family RTC – Real-Time Counter 14.3 Register Synchronization 19.6.9 Additional Features 19.6.9.1 Periodic Events The RTC prescaler can generate events at periodic intervals, allowing flexible system tick creation. Any of the upper eight bits of the prescaler (bits 2 to 9) can be the source of an event. When one of the eight Periodic Event Output bits in the Event Control register (EVCTRL.PEREO[n=0..
PAGE 265
SAM D21 Family RTC – Real-Time Counter 19.7 Register Summary The register mapping depends on the Operating Mode bits in the Control register (CTRL.MODE). The register summary is presented for each of the three modes. Table 19-1. MODE0 - Mode Register Summary Offset Name Bit Pos.
PAGE 266
SAM D21 Family RTC – Real-Time Counter ...........continued Offset Name Bit Pos. 0x08 INTFLAG 0x09 Reserved 7:0 OVF SYNCBUSY 0x0A STATUS 7:0 0x0B DBGCTRL 7:0 0x0C FREQCORR 7:0 SYNCRDY CMP1 CMP0 DBGRUN SIGN VALUE[6:0] 0x0D ...
PAGE 267
SAM D21 Family RTC – Real-Time Counter ...........continued Offset Name Bit Pos. 0x14 ... Reserved 0x17 0x18 0x19 0x1A 7:0 ALARM0 0x1B 0x1C 19.8 15:8 23:16 31:24 MASK MINUTE[1:0] SECOND[5:0] HOUR[3:0] MINUTE[5:2] MONTH[1:0] DAY[4:0] YEAR[5:0] 7:0 HOUR[4] MONTH[3:2] SEL[2:0] Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported.
PAGE 268
SAM D21 Family RTC – Real-Time Counter 19.8.
PAGE 269
SAM D21 Family RTC – Real-Time Counter Value 1 Description The counter is cleared on a Compare/Alarm 0 match. Bits 3:2 – MODE[1:0] Operating Mode These bits define the operating mode of the RTC. These bits are not synchronized. MODE[1:0] Name Description 0x0 COUNT32 Mode 0: 32-bit Counter 0x1 COUNT16 Mode 1: 16-bit Counter 0x2 CLOCK Mode 2: Clock/Calendar 0x3 Reserved Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRL.
PAGE 270
SAM D21 Family RTC – Real-Time Counter 19.8.
PAGE 271
SAM D21 Family RTC – Real-Time Counter MODE[1:0] Name Description 0x0 COUNT32 Mode 0: 32-bit Counter 0x1 COUNT16 Mode 1: 16-bit Counter 0x2 CLOCK Mode 2: Clock/Calendar 0x3 Reserved Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/ disabled. The value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.
PAGE 272
SAM D21 Family RTC – Real-Time Counter 19.8.
PAGE 273
SAM D21 Family RTC – Real-Time Counter Value 1 Description The counter is cleared on a Compare/Alarm 0 match. Bit 6 – CLKREP Clock Representation This bit is valid only in Mode 2 and determines how the hours are represented in the Clock Value (CLOCK) register. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Value 0 1 Description 24 Hour 12 Hour (AM/PM) Bits 3:2 – MODE[1:0] Operating Mode These bits define the operating mode of the RTC.
PAGE 274
SAM D21 Family RTC – Real-Time Counter Value 1 Description The reset operation is ongoing. © 2018 Microchip Technology Inc.
PAGE 275
SAM D21 Family RTC – Real-Time Counter 19.8.4 Read Request Name: Offset: Reset: Property: Bit READREQ 0x02 0x0010 - 15 14 RREQ RCONT Access W R/W Reset 0 0 Bit 7 6 13 12 11 5 4 3 10 9 8 2 1 0 ADDR[5:0] Access R R R R R R Reset 0 1 0 0 0 0 Bit 15 – RREQ Read Request Writing a zero to this bit has no effect. Writing a one to this bit requests synchronization of the register pointed to by the Address bit group (READREQ.
PAGE 276
SAM D21 Family RTC – Real-Time Counter 19.8.
PAGE 277
SAM D21 Family RTC – Real-Time Counter 19.8.
PAGE 278
SAM D21 Family RTC – Real-Time Counter 19.8.
PAGE 279
SAM D21 Family RTC – Real-Time Counter 19.8.8 Interrupt Enable Clear - MODE0 Name: Offset: Reset: Property: Bit Access Reset INTENCLR 0x06 0x00 Write-Protected 7 6 OVF SYNCRDY 5 4 3 2 1 CMP0 0 R/W R/W R/W 0 0 0 Bit 7 – OVF Overflow Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt. Value 0 1 Description The Overflow interrupt is disabled.
PAGE 280
SAM D21 Family RTC – Real-Time Counter 19.8.9 Interrupt Enable Clear - MODE1 Name: Offset: Reset: Property: Bit Access Reset INTENCLR 0x06 0x00 Write-Protected 7 6 1 0 OVF SYNCRDY 5 4 3 2 CMPx CMPx R/W R/W R/W R/W 0 0 0 0 Bit 7 – OVF Overflow Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt. Value 0 1 Description The Overflow interrupt is disabled.
PAGE 281
SAM D21 Family RTC – Real-Time Counter 19.8.10 Interrupt Enable Clear - MODE2 Name: Offset: Reset: Property: Bit Access Reset INTENCLR 0x06 0x00 Write-Protected 7 6 OVF SYNCRDY 5 4 3 2 1 ALARM0 0 R/W R/W R/W 0 0 0 Bit 7 – OVF Overflow Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt. Value 0 1 Description The Overflow interrupt is disabled.
PAGE 282
SAM D21 Family RTC – Real-Time Counter 19.8.11 Interrupt Enable Set - MODE0 Name: Offset: Reset: Property: Bit Access Reset INTENSET 0x07 0x00 Write-Protected 7 6 OVF SYNCRDY 5 4 3 2 1 CMP0 0 R/W R/W R/W 0 0 0 Bit 7 – OVF Overflow Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the Overflow Interrupt Enable bit and enable the Overflow interrupt. Value 0 1 Description The overflow interrupt is disabled. The overflow interrupt is enabled.
PAGE 283
SAM D21 Family RTC – Real-Time Counter 19.8.12 Interrupt Enable Set - MODE1 Name: Offset: Reset: Property: Bit Access Reset INTENSET 0x07 0x00 Write-Protected 7 6 1 0 OVF SYNCRDY 5 4 3 2 CMPx CMPx R/W R/W R/W R/W 0 0 0 0 Bit 7 – OVF Overflow Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the Overflow interrupt bit and enable the Overflow interrupt. Value 0 1 Description The overflow interrupt is disabled.
PAGE 284
SAM D21 Family RTC – Real-Time Counter 19.8.13 Interrupt Enable Set - MODE2 Name: Offset: Reset: Property: Bit Access Reset INTENSET 0x07 0x00 Write-Protected 7 6 OVF SYNCRDY 5 4 3 2 1 ALARM0 0 R/W R/W R/W 0 0 0 Bit 7 – OVF Overflow Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the Overflow Interrupt Enable bit and enable the Overflow interrupt. Value 0 1 Description The overflow interrupt is disabled. The overflow interrupt is enabled.
PAGE 285
SAM D21 Family RTC – Real-Time Counter 19.8.14 Interrupt Flag Status and Clear - MODE0 Name: Offset: Reset: Property: Bit Access Reset INTFLAG 0x08 0x00 - 7 6 OVF SYNCRDY 5 4 3 2 1 CMP0 0 R/W R/W R/W 0 0 0 Bit 7 – OVF Overflow This flag is cleared by writing a one to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is one. Writing a zero to this bit has no effect.
PAGE 286
SAM D21 Family RTC – Real-Time Counter 19.8.15 Interrupt Flag Status and Clear - MODE1 Name: Offset: Reset: Property: Bit Access Reset INTFLAG 0x08 0x00 - 7 6 1 0 OVF SYNCRDY 5 4 3 2 CMPx CMPx R/W R/W R/W R/W 0 0 0 0 Bit 7 – OVF Overflow This flag is cleared by writing a one to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is one. Writing a zero to this bit has no effect.
PAGE 287
SAM D21 Family RTC – Real-Time Counter 19.8.16 Interrupt Flag Status and Clear - MODE2 Name: Offset: Reset: Property: Bit Access Reset INTFLAG 0x08 0x00 - 7 6 OVF SYNCRDY 5 4 3 2 1 ALARM0 0 R/W R/W R/W 0 0 0 Bit 7 – OVF Overflow This flag is cleared by writing a one to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is one. Writing a zero to this bit has no effect.
PAGE 288
SAM D21 Family RTC – Real-Time Counter 19.8.17 Status Name: Offset: Reset: Property: Bit 7 STATUS 0x0A 0x00 - 6 5 4 3 2 1 0 SYNCBUSY Access R Reset 0 Bit 7 – SYNCBUSY Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. © 2018 Microchip Technology Inc.
PAGE 289
SAM D21 Family RTC – Real-Time Counter 19.8.18 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x0B 0x00 - 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Run During Debug This bit is not reset by a software reset. Writing a zero to this bit causes the RTC to halt during debug mode. Writing a one to this bit allows the RTC to continue normal operation during debug mode. © 2018 Microchip Technology Inc.
PAGE 290
SAM D21 Family RTC – Real-Time Counter 19.8.19 Frequency Correction Name: Offset: Reset: Property: Bit 7 FREQCORR 0x0C 0x00 Write-Protected, Write-Synchronized 6 5 4 SIGN Access Reset 3 2 1 0 VALUE[6:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 – SIGN Correction Sign Value 0 1 Description The correction value is positive, i.e., frequency will be decreased. The correction value is negative, i.e., frequency will be increased.
PAGE 291
SAM D21 Family RTC – Real-Time Counter 19.8.
PAGE 292
SAM D21 Family RTC – Real-Time Counter 19.8.21 Counter Value - MODE1 Name: Offset: Reset: Property: Bit 15 COUNT 0x10 0x0000 Read-Synchronized, Write-Protected, Write-Synchronized 14 13 12 11 10 9 8 COUNT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 – COUNT[15:0] Counter Value These bits define the value of the 16-bit RTC counter.
PAGE 293
SAM D21 Family RTC – Real-Time Counter 19.8.
PAGE 294
SAM D21 Family RTC – Real-Time Counter Table 19-4. Hour HOUR[4:0] CLOCK.HOUR[4] 0 0x00 - 0x17 Hour (0 - 23) 0x18 - 0x1F Reserved 1 0 1 CLOCK.HOUR[3:0] Description 0x0 Reserved 0x1 - 0xC AM Hour (1 - 12) 0xD - 0xF Reserved 0x0 Reserved 0x1 - 0xC PM Hour (1 - 12) 0xF - 0xF Reserved Bits 11:6 – MINUTE[5:0] Minute 0 – 59. Bits 5:0 – SECOND[5:0] Second 0– 59. © 2018 Microchip Technology Inc.
PAGE 295
SAM D21 Family RTC – Real-Time Counter 19.8.23 Counter Period - MODE1 Name: Offset: Reset: Property: Bit 15 PER 0x14 0x0000 Write-Protected, Write-Synchronized 14 13 12 11 10 9 8 PER[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PER[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 – PER[15:0] Counter Period These bits define the value of the 16-bit RTC period.
PAGE 296
SAM D21 Family RTC – Real-Time Counter 19.8.
PAGE 297
SAM D21 Family RTC – Real-Time Counter 19.8.25 Compare n Value - MODE1 Name: Offset: Reset: Property: Bit 15 COMPn 0x18+n*0x2 [n=0..
PAGE 298
SAM D21 Family RTC – Real-Time Counter 19.8.26 Alarm 0 Value - MODE2 Name: Offset: Reset: Property: ALARM0 0x18 0x00000000 Write-Protected, Write-Synchronized The 32-bit value of ALARM0 is continuously compared with the 32-bit CLOCK value, based on the masking set by MASKn.SEL. When a match occurs, the Alarm 0 interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.ALARMn) is set on the next counter cycle, and the counter is cleared if CTRL.MATCHCLR is one.
PAGE 299
SAM D21 Family RTC – Real-Time Counter 19.8.27 Alarm n Mask - MODE2 Name: Offset: Reset: Property: Bit MASK 0x1C 0x00 Write-Protected, Write-Synchronized 7 6 5 4 3 2 1 0 SEL[2:0] Access R/W R/W R/W 0 0 0 Reset Bits 2:0 – SEL[2:0] Alarm Mask Selection These bits define which bit groups of Alarm n are valid.
PAGE 300
SAM D21 Family DMAC – Direct Memory Access Controller 20. DMAC – Direct Memory Access Controller 20.1 Overview The Direct Memory Access Controller (DMAC) contains both a Direct Memory Access (DMA) engine and a Cyclic Redundancy Check (CRC) engine. The DMAC can transfer data between memories and peripherals and thus off-load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time.
PAGE 301
SAM D21 Family DMAC – Direct Memory Access Controller • • • • • • • • • Up to 12 Channels: – Enable 12 independent transfers – Automatic descriptor fetch for each channel – Suspend/resume operation support for each channel Flexible Arbitration Scheme: – 4 configurable priority levels for each channel – Fixed or round-robin priority scheme within each priority level From 1 to 256KB Data Transfer in a Single Block Transfer Multiple Addressing Modes: – Static – Configurable increment scheme Optional Int
PAGE 302
SAM D21 Family DMAC – Direct Memory Access Controller 20.3 Block Diagram Figure 20-1. DMAC Block Diagram CPU M AHB/APB Bridge SRAM Write-back M Data Transfer S S Descriptor Fetch HIGH SPEED BUS MATRIX DMAC MASTER Fetch Engine DMA Channels Channel n Transfer Triggers n n Channel 1 Channel 0 Interrupts Arbiter Active Channel Interrupt / Events Events CRC Engine 20.4 Signal Description Not applicable. 20.
PAGE 303
SAM D21 Family DMAC – Direct Memory Access Controller An AHB clock (CLK_DMAC_AHB) is required to clock the DMAC. This clock must be configured and enabled in the power manager before using the DMAC, and the default state of CLK_DMAC_AHB can be found in Peripheral Clock Masking. This bus clock (CLK_DMAC_APB) is always synchronous to the module clock (CLK_DMAC_AHB), but can be divided by a prescaler and may run even when the module clock is turned off. Related Links 16.6.2.6 Peripheral Clock Masking 20.5.
PAGE 304
SAM D21 Family DMAC – Direct Memory Access Controller 20.6.1.1 DMA The DMAC can transfer data between memories and peripherals without interaction from the CPU. The data transferred by the DMAC are called transactions, and these transactions can be split into smaller data transfers. The following figure shows the relationship between the different transfer sizes: Figure 20-2.
PAGE 305
SAM D21 Family DMAC – Direct Memory Access Controller 20.6.2 Basic Operation 20.6.2.1 Initialization The following DMAC registers are enable-protected, meaning that they can only be written when the DMAC is disabled (CTRL.DMAENABLE=0): • • Descriptor Base Memory Address register (BASEADDR) Write-Back Memory Base Address register (WRBADDR) The following DMAC bit is enable-protected, meaning that it can only be written when both the DMAC and CRC are disabled (CTRL.DMAENABLE=0 and CTRL.
PAGE 306
SAM D21 Family DMAC – Direct Memory Access Controller – – – – The transfer descriptor must be made valid by writing a one to the Valid bit in the Block Transfer Control register (BTCTRL.
PAGE 307
SAM D21 Family DMAC – Direct Memory Access Controller The write-back memory section is the section where the DMAC stores the transfer descriptors for the ongoing block transfers. WRBADDR points to the ongoing transfer descriptor of channel 0. All ongoing transfer descriptors will be stored in a contiguous memory section where the transfer descriptors are ordered according to their channel number. The figure below shows an example of linked descriptors on DMA channel 0.
PAGE 308
SAM D21 Family DMAC – Direct Memory Access Controller 20.6.2.4 Arbitration If a DMA channel is enabled and not suspended when it receives a transfer trigger, it will send a transfer request to the arbiter. When the arbiter receives the transfer request it will include the DMA channel in the queue of channels having pending transfers, and the corresponding Pending Channel x bit in the Pending Channels registers (PENDCH.PENDCHx) will be set.
PAGE 309
SAM D21 Family DMAC – Direct Memory Access Controller a channel with a lower priority level number. Each priority level x is enabled by setting the corresponding Priority Level x Enable bit in the Control register (CTRL.LVLENx=1). Within each priority level the DMAC's arbiter can be configured to prioritize statically or dynamically: Static Arbitration within a priority level is selected by writing a '0' to the Level x Round-Robin Scheduling Enable bit in the Priority Control 0 register (PRICTRL0.RRLVLENx).
PAGE 310
SAM D21 Family DMAC – Direct Memory Access Controller Figure 20-6. Dynamic (Round-Robin) Priority Scheduling Channel x last acknowledge request Channel (x+1) last acknowledge request Channel 0 Channel 0 . . . Channel x Channel x+1 Lowest Priority Channel x Highest Priority Channel x+1 Lowest Priority Channel x+2 Highest Priority . . . Channel N Channel N 20.6.2.
PAGE 311
SAM D21 Family DMAC – Direct Memory Access Controller 20.6.2.6 Transfer Triggers and Actions A DMA transfer through a DMA channel can be started only when a DMA transfer request is detected, and the DMA channel has been granted access to the DMA. A transfer request can be triggered from software, from a peripheral, or from an event. There are dedicated Trigger Source selections for each DMA Channel Control B (CHCTRLB.TRIGSRC).
PAGE 312
SAM D21 Family DMAC – Direct Memory Access Controller ongoing one is done. Only one pending transfer can be kept per channel. If the trigger source generates more transfer requests while one is already pending, the additional ones will be lost. All channels pending status flags are also available in the Pending Channels register (PENDCH). When the transfer starts, the corresponding Channel Busy status flag is set in Channel Status register (CHSTATUS.BUSY).
PAGE 313
SAM D21 Family DMAC – Direct Memory Access Controller Figure 20-8. Source Address Increment SRC Data Buffer a b c d e f Incrementation for the destination address of a block transfer is enabled by setting the Destination Address Incrementation Enable bit in the Block Transfer Control register (BTCTRL.DSTINC=1). The step size of the incrementation is configurable by clearing BTCTRL.STEPSEL=0 and writing BTCTRL.STEPSIZE to the desired step size. If BTCTRL.
PAGE 314
SAM D21 Family DMAC – Direct Memory Access Controller Figure 20-9. Destination Address Increment DST Data Buffer a b c d 20.6.2.8 Error Handling If a bus error is received from an AHB slave during a DMA data transfer, the corresponding active channel is disabled and the corresponding Channel Transfer Error Interrupt flag in the Channel Interrupt Status and Clear register (CHINTFLAG.TERR) is set. If enabled, the optional transfer error interrupt is generated.
PAGE 315
SAM D21 Family DMAC – Direct Memory Access Controller – – – – 5. 6. 7. Set the next descriptor address (DESCADDR) Set the destination address (DSTADDR) Set the source address (SRCADDR) Configure the block transfer control (BTCTRL) including • Optionally enable the Suspend block action • Set the descriptor VALID bit Clear the VALID bit for the existing list and for the descriptor which has to be updated. Read DESCADDR from the Write-Back memory.
PAGE 316
SAM D21 Family DMAC – Direct Memory Access Controller By configuring the block action to suspend by writing Block Action bit group in the Block Transfer Control register (BTCTRL.BLOCKACT is 0x2 or 0x3), the DMA channel will be suspended after it has completed a block transfer. The DMA channel will be kept enabled and will be able to receive transfer triggers, but it will be removed from the arbitration scheme. If an invalid transfer descriptor (BTCTRL.
PAGE 317
SAM D21 Family DMAC – Direct Memory Access Controller Normal Transfer The event input is used to trigger a beat or burst transfer on peripherals. The event is acknowledged as soon as the event is received. When received, both the Channel Pending status bit in the Channel Status register (CHSTATUS.PEND) and the corresponding Channel n bit in the Pending Channels register (20.8.13 PENDCH.PENDCHn) are set. If the event is received while the channel is pending, the event trigger is lost.
PAGE 318
SAM D21 Family DMAC – Direct Memory Access Controller Figure 20-12. Periodic Event with Beat Peripheral Triggers Trigger Lost Trigger Lost Event Peripheral Trigger PENDCHn Block Transfer Data Transfer BEAT Conditional Transfer The event input is used to trigger a conditional transfer on peripherals with pending transfer requests.
PAGE 319
SAM D21 Family DMAC – Direct Memory Access Controller Figure 20-14. Conditional Block Transfer with Beat Peripheral Triggers Event Peripheral Trigger PENDCHn Block Transfer Data Transfer Block Transfer BEAT BEAT BEAT BEAT Channel Suspend The event input is used to suspend an ongoing channel operation. The event is acknowledged when the current AHB access is completed. For further details on Channel Suspend, refer to 20.6.3.2 Channel Suspend.
PAGE 320
SAM D21 Family DMAC – Direct Memory Access Controller Figure 20-15. Event Output Generation Beat Event Output Block Transfer Data Transfer Block Transfer BEAT BEAT BEAT BEAT Event Output Block Event Output Block Transfer Data Transfer BEAT Block Transfer BEAT BEAT BEAT Event Output 20.6.3.6 Aborting Transfers Transfers on any channel can be aborted gracefully by software by disabling the corresponding DMA channel.
PAGE 321
SAM D21 Family DMAC – Direct Memory Access Controller • • CRC-16: – Polynomial: x16+ x12+ x5+ 1 – Hex value: 0x1021 CRC-32: – Polynomial: x32+x26+ x23+ x22+x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x + 1 – Hex value: 0x04C11DB7 The data source for the CRC engine can either be one of the DMA channels or the APB bus interface, and must be selected by writing to the CRC Input Source bits in the CRC Control register (CRCCTRL.CRCSRC).
PAGE 322
SAM D21 Family DMAC – Direct Memory Access Controller CRC on CRC-16 or CRC-32 calculations can be performed on data passing through any DMA DMA channel. Once a DMA channel is selected as the source, the CRC engine will continuously data generate the CRC on the data passing through the DMA channel. The checksum is available for readout once the DMA transaction is completed or aborted. A CRC can also be generated on SRAM, Flash, or I/O memory by passing these data through a DMA channel.
PAGE 323
SAM D21 Family DMAC – Direct Memory Access Controller 11.2 Nested Vector Interrupt Controller 20.6.6 Events The DMAC can generate the following output events: • Channel (CH): Generated when a block transfer for a given channel has been completed, or when a beat transfer within a block transfer for a given channel has been completed. Refer to Event Output Selection for details. Setting the Channel Event Output Enable bit (CHEVCTRLx.
PAGE 324
SAM D21 Family DMAC – Direct Memory Access Controller 20.7 Register Summary Offset Name 0x00 CTRL 0x02 0x04 CRCCTRL CRCDATAIN Bit Pos.
PAGE 325
SAM D21 Family DMAC – Direct Memory Access Controller ...........continued Offset Name Bit Pos. 7:0 0x2C PENDCH PENDCH7 PENDCH6 PENDCH5 PENDCH4 15:8 PENDCH3 PENDCH2 PENDCH1 PENDCH0 PENDCH11 PENDCH10 PENDCH9 PENDCH8 LVLEXx LVLEXx LVLEXx LVLEXx ENABLE SWRST 23:16 31:24 7:0 0x30 ACTIVE 15:8 ABUSY ID[4:0] 23:16 BTCNT[7:0] 31:24 BTCNT[15:8] 7:0 0x34 BASEADDR 15:8 23:16 31:24 7:0 0x38 WRBADDR 15:8 23:16 31:24 0x3C ...
PAGE 326
SAM D21 Family DMAC – Direct Memory Access Controller Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. © 2018 Microchip Technology Inc.
PAGE 327
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.
PAGE 328
SAM D21 Family DMAC – Direct Memory Access Controller Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit when both the DMAC and the CRC module are disabled (DMAENABLE and CRCENABLE are '0') resets all registers in the DMAC (except DBGCTRL) to their initial state. If either the DMAC or CRC module is enabled, the Reset request will be ignored and the DMAC will return an access error. Value 0 1 Description There is no Reset operation ongoing.
PAGE 329
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.2 CRC Control Name: Offset: Reset: Property: Bit CRCCTRL 0x02 0x0000 PAC Write-Protection, Enable-Protected 15 14 13 12 11 10 9 8 CRCSRC[5:0] Access Reset Bit 7 6 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 5 4 3 1 0 2 CRCPOLY[1:0] Access Reset CRCBEATSIZE[1:0] R/W R/W R/W R/W 0 0 0 0 Bits 13:8 – CRCSRC[5:0] CRC Input Source These bits select the input source for generating the CRC, as shown in the table below.
PAGE 330
SAM D21 Family DMAC – Direct Memory Access Controller Value Name 0x1 CRC32 0x2-0x3 Description CRC32 (IEEE 802.3) Reserved Bits 1:0 – CRCBEATSIZE[1:0] CRC Beat Size These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface. Value 0x0 0x1 0x2 0x3 Name BYTE HWORD WORD © 2018 Microchip Technology Inc.
PAGE 331
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.
PAGE 332
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.4 CRC Checksum Name: Offset: Reset: Property: CRCCHKSUM 0x08 0x00000000 PAC Write-Protection, Enable-Protected The CRCCHKSUM represents the 16- or 32-bit checksum value and the generated CRC. The register is reset to zero by default, but it is possible to reset all bits to one by writing the CRCCHKSUM register directly. It is possible to write this register only when the CRC module is disabled.
PAGE 333
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.5 CRC Status Name: Offset: Reset: Property: Bit 7 CRCSTATUS 0x0C 0x00 PAC Write-Protection 6 5 4 3 2 1 0 CRCZERO CRCBUSY Access R R/W Reset 0 0 Bit 1 – CRCZERO CRC Zero This bit is cleared when a new CRC source is selected. This bit is set when the CRC generation is complete and the CRC Checksum is zero.
PAGE 334
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.6 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x0D 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run This bit is not reset by a software reset. This bit controls the functionality when the CPU is halted by an external debugger. Value 0 1 Description The DMAC is halted when the CPU is halted by an external debugger.
PAGE 335
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.7 Quality of Service Control Name: Offset: Reset: Property: Bit QOSCTRL 0x0E 0x2A PAC Write-Protection 7 6 5 4 3 DQOS[1:0] Access 2 1 FQOS[1:0] 0 WRBQOS[1:0] R/W R/W R/W R/W R/W R/W 1 0 1 0 1 0 Reset Bits 5:4 – DQOS[1:0] Data Transfer Quality of Service These bits define the memory priority access during the data transfer operation.
PAGE 336
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.
PAGE 337
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.
PAGE 338
SAM D21 Family DMAC – Direct Memory Access Controller Value 0 1 Description Static arbitration scheme for channels with level 2 priority. Round-robin arbitration scheme for channels with level 2 priority. Bits 19:16 – LVLPRI2[3:0] Level 2 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN2=1) for priority level 2, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 2.
PAGE 339
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.10 Interrupt Pending Name: Offset: Reset: Property: INTPEND 0x20 0x0000 - This register allows the user to identify the lowest DMA channel with pending interrupt.
PAGE 340
SAM D21 Family DMAC – Direct Memory Access Controller Bits 3:0 – ID[3:0] Channel ID These bits store the lowest channel number with pending interrupts. The number is valid if Suspend (SUSP), Transfer Complete (TCMPL) or Transfer Error (TERR) bits are set. The Channel ID field is refreshed when a new channel (with channel number less than the current one) with pending interrupts is detected, or when the application clears the corresponding channel interrupt sources.
PAGE 341
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.11 Interrupt Status Name: Offset: Reset: Property: Bit INTSTATUS 0x24 0x00000000 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Access R R R R Reset 0 0 0 0 3 2 1 0 Access Reset Bit Access Reset Bit CHINTn[11:8] Bit 7 6 5 4 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 CHINTn[7:0] Bits 11:0 – CHINTn[11:0] Channel n Pending Interrupt [n=11..
PAGE 342
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.12 Busy Channels Name: Offset: Reset: Property: Bit BUSYCH 0x28 0x00000000 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Access R R R R Reset 0 0 0 0 3 2 1 0 Access Reset Bit Access Reset Bit BUSYCHn[11:8] Bit 7 6 5 4 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 BUSYCHn[7:0] Bits 11:0 – BUSYCHn[11:0] Busy Channel n [x=11..
PAGE 343
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.
PAGE 344
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.
PAGE 345
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.15 Descriptor Memory Section Base Address Name: Offset: Reset: Property: Bit BASEADDR 0x34 0x00000000 PAC Write-Protection, Enable-Protected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset © 2018 Microchip Technology Inc.
PAGE 346
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.16 Write-Back Memory Section Base Address Name: Offset: Reset: Property: Bit WRBADDR 0x38 0x00000000 PAC Write-Protection, Enable-Protected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset © 2018 Microchip Technology Inc.
PAGE 347
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.17 Channel ID Name: Offset: Reset: Property: Bit 7 CHID 0x3F 0x00 - 6 5 4 3 2 1 0 ID[3:0] Access Reset R/W R/W R/W R/W 0 0 0 0 Bits 3:0 – ID[3:0] Channel ID These bits define the channel number that will be affected by the channel registers (CH*). Before reading or writing a channel register, the channel ID bit group must be written first. © 2018 Microchip Technology Inc.
PAGE 348
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.18 Channel Control A Name: Offset: Reset: Property: CHCTRLA 0x40 0x00 PAC Write-Protection, Enable-Protected This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
PAGE 349
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.19 Channel Control B Name: Offset: Reset: Property: CHCTRLB 0x44 0x00000000 PAC Write Protection, Enable-Protected This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
PAGE 350
SAM D21 Family DMAC – Direct Memory Access Controller ...........continued TRIGACT[1:0] Name Description 0x2 BEAT One trigger required for each beat transfer 0x3 TRANSACTION One trigger required for each transaction Bits 13:8 – TRIGSRC[5:0] Trigger Source These bits define the peripheral trigger which is source of the transfer. For details on trigger selection and trigger modes, refer to Transfer Triggers and Actions and CHCTRLB.TRIGACT.
PAGE 351
SAM D21 Family DMAC – Direct Memory Access Controller Value 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 Name TC7 MC0 TC7 MC1 ADC RESRDY DAC EMPTY I2S RX 0 I2S RX 1 I2S TX 0 I2S TX 0 OVF TCC3 MC0 TCC3 MC1 TCC3 MC2 TCC3 MC3 Description TC7 Match/Compare 0 Trigger TC7 Match/Compare 1 Trigger ADC Result Ready Trigger DAC Empty Trigger I2S RX 0 Trigger I2S RX 1 Trigger I2S TX 0 Trigger I2S TX 1 Trigger TCC3 Overflow Trigger TCC3 Match/Compare 0 Trigger TCC3 Match/Compare 1 Trigger Match/Co
PAGE 352
SAM D21 Family DMAC – Direct Memory Access Controller These bits are available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.
PAGE 353
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.20 Channel Interrupt Enable Clear Name: Offset: Reset: Property: CHINTENCLR 0x4C 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Channel Interrupt Enable Set (CHINTENSET) register. This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
PAGE 354
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.21 Channel Interrupt Enable Set Name: Offset: Reset: Property: CHINTENSET 0x4D 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Channel Interrupt Enable Clear (CHINTENCLR) register. This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
PAGE 355
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.22 Channel Interrupt Flag Status and Clear Name: Offset: Reset: Property: CHINTFLAG 0x4E 0x00 - This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 7 6 5 4 3 2 1 0 SUSP TCMPL TERR R/W R/W R/W 0 0 0 Access Reset Bit 2 – SUSP Channel Suspend This flag is cleared by writing a '1' to it.
PAGE 356
SAM D21 Family DMAC – Direct Memory Access Controller 20.8.23 Channel Status Name: Offset: Reset: Property: CHSTATUS 0x4F 0x00 - This register affects the DMA channel that is selected in the Channel ID register (CHID.ID). Bit 7 6 5 4 3 2 1 0 FERR BUSY PEND Access R R R Reset 0 0 0 Bit 2 – FERR Channel Fetch Error This bit is cleared when a software resume command is executed. This bit is set when an invalid descriptor is fetched.
PAGE 357
SAM D21 Family DMAC – Direct Memory Access Controller 20.9 Register Summary - SRAM Offset Name 0x00 BTCTRL 0x02 0x04 0x08 0x0C 20.10 BTCNT SRCADDR DSTADDR DESCADDR Bit Pos.
PAGE 358
SAM D21 Family DMAC – Direct Memory Access Controller 20.10.1 Block Transfer Control Name: Offset: Property: BTCTRL 0x00 - The BTCTRL register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 15 14 13 STEPSIZE[2:0] 12 11 10 STEPSEL DSTINC SRCINC 9 4 3 2 8 BEATSIZE[1:0] Access Reset Bit 7 6 5 BLOCKACT[1:0] 1 EVOSEL[1:0] 0 VALID Access Reset Bits 15:13 – STEPSIZE[2:0] Address Increment Step Size These bits select the address increment step size.
PAGE 359
SAM D21 Family DMAC – Direct Memory Access Controller Bit 10 – SRCINC Source Address Increment Enable Writing a '0' to this bit will disable the source address incrementation. The address will be kept fixed during the data transfer. Writing a '1' to this bit will enable the source address incrementation. By default, the source address is incremented by 1. If the STEPSEL bit is set, flexible step-size settings are available in the STEPSIZE register.
PAGE 360
SAM D21 Family DMAC – Direct Memory Access Controller Value 0 1 Description The descriptor is not valid. The descriptor is valid. © 2018 Microchip Technology Inc.
PAGE 361
SAM D21 Family DMAC – Direct Memory Access Controller 20.10.2 Block Transfer Count Name: Offset: Property: BTCNT 0x02 - The BTCNT register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10 Bit 15 14 13 12 11 10 9 8 3 2 1 0 BTCNT[15:8] Access Reset Bit 7 6 5 4 BTCNT[7:0] Access Reset Bits 15:0 – BTCNT[15:0] Block Transfer Count This bit group holds the 16-bit block transfer count.
PAGE 362
SAM D21 Family DMAC – Direct Memory Access Controller 20.10.
PAGE 363
SAM D21 Family DMAC – Direct Memory Access Controller 20.10.
PAGE 364
SAM D21 Family DMAC – Direct Memory Access Controller 20.10.
PAGE 365
SAM D21 Family EIC – External Interrupt Controller 21. EIC – External Interrupt Controller 21.1 Overview The External Interrupt Controller (EIC) allows external pins to be configured as interrupt lines. Each interrupt line can be individually masked and can generate an interrupt on rising, falling, or both edges, or on high or low levels. Each external pin has a configurable filter to remove spikes.
PAGE 366
SAM D21 Family EIC – External Interrupt Controller 21.4 Signal Description Signal Name Type Description EXTINT[15..0] Digital Input External interrupt pin NMI Digital Input Non-maskable interrupt pin One signal may be available on several pins. Related Links 7. I/O Multiplexing and Considerations 21.5 Product Dependencies In order to use this EIC, other parts of the system must be configured correctly, as described below. 21.5.
PAGE 367
SAM D21 Family EIC – External Interrupt Controller 21.5.5 Interrupts There are several interrupt request lines, at least one for the external interrupts (EXTINT) and one for non-maskable interrupt (NMI). The EXTINT interrupt request line is connected to the interrupt controller. Using the EIC interrupt requires the interrupt controller to be configured first. The NMI interrupt request line is also connected to the interrupt controller, but does not require the interrupt to be configured. Related Links 11.
PAGE 368
SAM D21 Family EIC – External Interrupt Controller 21.6.2 Basic Operation 21.6.2.1 Initialization The EIC must be initialized in the following order: 1. Enable CLK_EIC_APB 2. If edge detection or filtering is required, GCLK_EIC must be enabled 3. Write the EIC configuration registers (EVCTRL, WAKEUP, CONFIGy) 4. Enable the EIC To use NMI, GCLK_EIC must be enabled after EIC configuration (NMICTRL). 21.6.2.
PAGE 369
SAM D21 Family EIC – External Interrupt Controller If filtering or edge detection is enabled, the EIC automatically requests the GCLK_EIC to operate (GCLK_EIC must be enabled in the GCLK module, see GCLK – Generic Clock Controller for details). If level detection is enabled, GCLK_EIC is not required, but interrupt and events can still be generated. When an external interrupt is configured for level detection and when filtering is disabled, detection is done asynchronously.
PAGE 370
SAM D21 Family EIC – External Interrupt Controller When an NMI is detected, the non-maskable interrupt flag in the NMI Flag Status and Clear register is set (NMIFLAG.NMI). NMI interrupt generation is always enabled, and NMIFLAG.NMI generates an interrupt request when set. 21.6.5 DMA Operation Not applicable. 21.6.6 Interrupts The EIC has the following interrupt sources: • • External interrupt pins (EXTINTx). See 21.6.2 Basic Operation. Non-maskable interrupt pin (NMI). See 21.6.4 Additional Features.
PAGE 371
SAM D21 Family EIC – External Interrupt Controller Using WAKEUPEN[x]=1 with INTENSET=0 is not recommended. In sleep modes, an EXTINTx pin can wake up the device if the corresponding condition matches the configuration in CONFIGn register, and the corresponding bit in the Interrupt Enable Set register (INTENSET) is written to '1'. WAKEUP.WAKEUPEN[x]=1 can enable the wake-up from pin EXTINTx. Figure 21-3.
PAGE 372
SAM D21 Family EIC – External Interrupt Controller 21.7 Register Summary Offset Name Bit Pos.
PAGE 373
SAM D21 Family EIC – External Interrupt Controller 21.8.1 Control Name: Offset: Reset: Property: Bit 7 CTRL 0x00 0x00 Write-Protected, Write-Synchronized 6 5 4 3 Access Reset 2 1 0 ENABLE SWRST R/W R/W 0 0 Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/ disabled. The value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.
PAGE 374
SAM D21 Family EIC – External Interrupt Controller 21.8.2 Status Name: Offset: Reset: Property: Bit 7 STATUS 0x01 0x00 - 6 5 4 3 2 1 0 SYNCBUSY Access R Reset 0 Bit 7 – SYNCBUSY Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. © 2018 Microchip Technology Inc.
PAGE 375
SAM D21 Family EIC – External Interrupt Controller 21.8.3 Non-Maskable Interrupt Control Name: Offset: Reset: Property: Bit NMICTRL 0x02 0x00 Write-Protected 7 6 5 4 3 2 NMIFILTEN Access Reset 1 0 NMISENSE[2:0] R/W R/W R/W R/W 0 0 0 0 Bit 3 – NMIFILTEN Non-Maskable Interrupt Filter Enable Value 0 1 Description NMI filter is disabled. NMI filter is enabled. Bits 2:0 – NMISENSE[2:0] Non-Maskable Interrupt Sense These bits define on which edge or level the NMI triggers.
PAGE 376
SAM D21 Family EIC – External Interrupt Controller 21.8.4 Non-Maskable Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 NMIFLAG 0x03 0x00 - 6 5 4 3 2 1 0 NMI Access R/W Reset 0 Bit 0 – NMI Non-Maskable Interrupt This flag is cleared by writing a one to it. This flag is set when the NMI pin matches the NMI sense configuration, and will generate an interrupt request. Writing a zero to this bit has no effect. Writing a one to this bit clears the non-maskable interrupt flag.
PAGE 377
SAM D21 Family EIC – External Interrupt Controller 21.8.
PAGE 378
SAM D21 Family EIC – External Interrupt Controller 21.8.
PAGE 379
SAM D21 Family EIC – External Interrupt Controller 21.8.
PAGE 380
SAM D21 Family EIC – External Interrupt Controller 21.8.
PAGE 381
SAM D21 Family EIC – External Interrupt Controller 21.8.
PAGE 382
SAM D21 Family EIC – External Interrupt Controller 21.8.
PAGE 383
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller 22. 22.1 NVMCTRL – Nonvolatile Memory Controller Overview Nonvolatile Memory (NVM) is a reprogrammable Flash memory that retains program and data storage even with power off. It embeds a main array and a separate smaller array intended for EEPROM emulation (RWWEE) that can be programmed while reading the main array. The NVM Controller (NVMCTRL) connects to the AHB and APB bus interfaces for system access to the NVM block.
PAGE 384
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller 22.4 Signal Description Not applicable. 22.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described in the following sections. 22.5.1 Power Management The NVMCTRL will continue to operate in any sleep mode where the selected source clock is running. The NVMCTRL interrupts can be used to wake up the device from sleep modes.
PAGE 385
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller • Status register (STATUS) Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description. Related Links 11.6 PAC - Peripheral Access Controller 22.5.6 Analog Connections Not applicable. 22.6 Functional Description 22.6.1 Principle of Operation The NVM Controller is a slave on the AHB and APB buses.
PAGE 386
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller Figure 22-3. NVM Memory Organization Calibration and Auxillary Space NVM Base Address + 0x00800000 RWWEE Address Space NVM Base Address + 0x00400000 NVM Base Address + NVM Size NVM Main Address Space NVM Base Address The lower rows in the NVM main address space can be allocated as a boot loader section by using the BOOTPROT fuses, and the upper rows can be allocated to EEPROM, as shown in the figure below.
PAGE 387
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller Figure 22-4. EEPROM and Boot Loader Allocation Related Links 10.2 Physical Memory Map 22.6.3 Region Lock Bits The NVM block is grouped into 16 equally sized regions. The region size is dependent on the Flash memory size, and is given in the table below. Each region has a dedicated lock bit preventing writing and erasing pages in the region. After production, all regions will be unlocked. Table 22-1.
PAGE 388
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller the Lock and Unlock commands. The current status of the lock can be determined by reading the LOCK register. To change the default lock/unlock setting for a region, the user configuration section of the auxiliary space must be written using the Write Auxiliary Page command. Writing to the auxiliary space will take effect after the next Reset. Therefore, a boot of the device is needed for changes in the lock/unlock setting to take effect.
PAGE 389
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller 22.6.4.2 RWWEE Read Reading from the RWW EEPROM address space is performed via the AHB bus by addressing the RWWEE address space directly. Read timings are similar to regular NVM read timings when access size is Byte or half-Word. The AHB data phase is twice as long in case of full-Word-size access.
PAGE 390
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller • When the last location in the page buffer is written, the page is automatically written to NVM main address space. INTFLAG.READY will be zero while programming is in progress and access through the AHB will be stalled. 22.6.4.4 Page Buffer Clear The page buffer is automatically set to all '1' after a page write is performed.
PAGE 391
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller Note: 1) Default value is 0x7. The EEPROM[2:0] bits indicate the EEPROM size, see the table below. The EEPROM resides in the upper rows of the NVM main address space and is writable, regardless of the region lock status. Table 22-3. EEPROM Size EEPROM[2:0] Rows Allocated to EEPROM EEPROM Size in Bytes 7 None 0 6 1 256 5 2 512 4 4 1024 3 8 2048 2 16 4096 1 32 8192 0 64 16384 Related Links 10.2 Physical Memory Map 22.6.
PAGE 392
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller 22.7 Register Summary Offset Name 0x00 CTRLA Bit Pos. 7:0 CMD[6:0] 15:8 CMDEX[7:0] 0x02 ... Reserved 0x03 7:0 0x04 CTRLB MANW RWS[3:0] 15:8 SLEEPPRM[1:0] 23:16 CACHEDIS READMODE[1:0] 31:24 0x08 PARAM 0x0C INTENCLR 7:0 NVMP[7:0] 15:8 NVMP[15:8] 23:16 31:24 RWWEEP[3:0] PSZ[2:0] RWWEEP[11:4] 7:0 ERROR READY 7:0 ERROR READY 7:0 ERROR READY LOAD PRM 0x0D ... Reserved 0x0F 0x10 INTENSET 0x11 ...
PAGE 393
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" and/or "Write-Synchronized" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. © 2018 Microchip Technology Inc.
PAGE 394
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller 22.8.
PAGE 395
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller ...........continued CMD[6:0] Group Configuration Description 0x06 WAP Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the Security bit is not set and only to the User Configuration Row. 0x07-0x0E - Reserved 0x0F - Reserved 0x1A-0x19 - Reserved 0x1A RWWEEER RWWEE Erase Row - Erases the row addressed by the ADDR register in the RWWEE array.
PAGE 396
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller 22.8.
PAGE 397
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller Bits 9:8 – SLEEPPRM[1:0] Power Reduction Mode during Sleep Indicates the Power Reduction Mode during sleep. Value 0x0 Name WAKEUPACCESS 0x1 WAKEUPINSTANT 0x2 0x3 Reserved DISABLED Description NVM block enters low-power mode when entering sleep. NVM block exits low-power mode upon first access. NVM block enters low-power mode when entering sleep. NVM block exits low-power mode when exiting sleep. Auto power reduction disabled.
PAGE 398
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller 22.8.
PAGE 399
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller 22.8.4 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x0C 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 5 4 3 Access Reset 2 1 0 ERROR READY R/W R/W 0 0 Bit 1 – ERROR Error Interrupt Enable Writing a '0' to this bit has no effect.
PAGE 400
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller 22.8.5 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x10 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 5 4 3 Access Reset 2 1 0 ERROR READY R/W R/W 0 0 Bit 1 – ERROR Error Interrupt Enable Writing a '0' to this bit has no effect.
PAGE 401
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller 22.8.6 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 INTFLAG 0x14 0x00 – 6 5 4 3 2 Access Reset 1 0 ERROR READY R/W R 0 0 Bit 1 – ERROR Error This flag is set on the occurrence of an NVME, LOCKE or PROGE error. This bit can be cleared by writing a '1' to its bit location. Value 0 1 Description No errors have been received since the last clear. At least one error has occurred since the last clear.
PAGE 402
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller 22.8.7 Status Name: Offset: Reset: Property: Bit 15 STATUS 0x18 0x0X00 – 14 13 12 11 10 9 8 SB Access R Reset x Bit 7 6 5 Access Reset 4 3 2 1 0 NVME LOCKE PROGE LOAD PRM R/W R/W R/W R/W R 0 0 0 0 0 Bit 8 – SB Security Bit Status Value 0 1 Description The Security bit is inactive. The Security bit is active. Bit 4 – NVME NVM Error This bit can be cleared by writing a '1' to its bit location.
PAGE 403
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller Bit 1 – LOAD NVM Page Buffer Active Loading This bit indicates that the NVM page buffer has been loaded with one or more words. Immediately after an NVM load has been performed, this flag is set. It remains set until a page write or a page buffer clear (PBCLR) command is given. This bit can be cleared by writing a '1' to its bit location. Bit 0 – PRM Power Reduction Mode This bit indicates the current NVM power reduction state.
PAGE 404
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller 22.8.
PAGE 405
SAM D21 Family NVMCTRL – Nonvolatile Memory Controller 22.8.9 Lock Section Name: Offset: Reset: Property: Bit 15 LOCK 0x20 0xXXXX – 14 13 12 11 10 9 8 LOCK[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LOCK[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 x Bits 15:0 – LOCK[15:0] Region Lock Bits To set or clear these bits, the CMD register must be used. Default state after erase will be unlocked (0x0000).
PAGE 406
SAM D21 Family PORT - I/O Pin Controller 23. PORT - I/O Pin Controller 23.1 Overview The IO Pin Controller (PORT) controls the I/O pins of the device. The I/O pins are organized in a series of groups, collectively referred to as a PORT group. Each PORT group can have up to 32 pins that can be configured and controlled individually or as a group. The number of PORT groups on a device may depend on the package/number of pins.
PAGE 407
SAM D21 Family PORT - I/O Pin Controller 23.3 Block Diagram Figure 23-1. PORT Block Diagram PORT Peripheral Mux Select Control Status Port Line Bundles IP Line Bundles PORTMUX and Pad Line Bundles I/O PADS Analog Pad Connections PERIPHERALS Digital Controls of Analog Blocks 23.4 ANALOG BLOCKS Signal Description Table 23-1.
PAGE 408
SAM D21 Family PORT - I/O Pin Controller has control over the output state of the pad, as well as the ability to read the current physical pad state. Refer to I/O Multiplexing and Considerations for details. Device-specific configurations may cause some lines (and the corresponding Pxy pin) not to be implemented. Related Links 7. I/O Multiplexing and Considerations 23.5.2 Power Management During Reset, all PORT lines are configured as inputs with input buffers, output buffers and pull disabled.
PAGE 409
SAM D21 Family PORT - I/O Pin Controller Related Links 11.6 PAC - Peripheral Access Controller 23.5.9 Analog Connections Analog functions are connected directly between the analog blocks and the I/O pads using analog buses. However, selecting an analog peripheral function for a given pin will disable the corresponding digital features of the pad. 23.5.10 CPU Local Bus The CPU local bus (IOBUS) is an interface that connects the CPU directly to the PORT.
PAGE 410
SAM D21 Family PORT - I/O Pin Controller 23.6.1 Principle of Operation Each PORT group of up to 32 pins is controlled by the registers in PORT, as described in the figure. These registers in PORT are duplicated for each PORT group, with increasing base addresses. The number of PORT groups may depend on the package/number of pins. Figure 23-3.
PAGE 411
SAM D21 Family PORT - I/O Pin Controller 23.6.2 Basic Operation 23.6.2.1 Initialization After reset, all standard function device I/O pads are connected to the PORT with outputs tri-stated and input buffers disabled, even if there is no clock running. However, specific pins, such as those used for connection to a debugger, may be configured differently, as required by their special function. 23.6.2.2 Operation Each I/O pin Pxy can be controlled by the registers in PORT.
PAGE 412
SAM D21 Family PORT - I/O Pin Controller The I/O pin configurations are described further in this chapter, and summarized in Table 23-2. 23.6.3.1 Pin Configurations Summary Table 23-2.
PAGE 413
SAM D21 Family PORT - I/O Pin Controller Figure 23-6. I/O Configuration - Totem-Pole Output with Disabled Input PULLEN PULLEN INEN DIR 0 0 1 DIR OUT IN INEN Figure 23-7. I/O Configuration - Totem-Pole Output with Enabled Input PULLEN PULLEN INEN DIR 0 1 1 PULLEN INEN DIR 1 0 0 DIR OUT IN INEN Figure 23-8. I/O Configuration - Output with Pull PULLEN DIR OUT IN INEN 23.6.3.4 Digital Functionality Disabled Neither Input nor Output functionality are enabled. Figure 23-9.
PAGE 414
SAM D21 Family PORT - I/O Pin Controller The following priority is adopted: 1. 2. ARM® CPU IOBUS (No wait tolerated) APB © 2018 Microchip Technology Inc.
PAGE 415
SAM D21 Family PORT - I/O Pin Controller 23.7 Register Summary The I/O pins are assembled in pin groups with up to 32 pins. Group 0 consists of the PA pins, and group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80.
PAGE 416
SAM D21 Family PORT - I/O Pin Controller ...........continued Offset 0x24 0x28 Name CTRL WRCONFIG Bit Pos. 7:0 SAMPLING[7:0] 15:8 SAMPLING[15:8] 23:16 SAMPLING[23:16] 31:24 SAMPLING[31:24] 7:0 PINMASK[7:0] 15:8 PINMASK[15:8] 23:16 31:24 PULLEN HWSEL WRPINCFG WRPMUX INEN PMUXEN PMUX[3:0] 0x2C ... Reserved 0x2F 0x30 PMUX0 7:0 PMUXO[3:0] PMUXE[3:0] 0x3F PMUX15 7:0 0x40 PINCFG0 7:0 DRVSTR PULLEN INEN PMUXEN PINCFG31 7:0 DRVSTR PULLEN INEN PMUXEN ...
PAGE 417
SAM D21 Family PORT - I/O Pin Controller 23.8.1 Data Direction Name: Offset: Reset: Property: DIR 0x00 0x00000000 PAC Write-Protection This register allows the user to configure one or more I/O pins as an input or output. This register can be manipulated without doing a read-modify-write operation by using the Data Direction Toggle (DIRTGL), Data Direction Clear (DIRCLR) and Data Direction Set (DIRSET) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins.
PAGE 418
SAM D21 Family PORT - I/O Pin Controller 23.8.2 Data Direction Clear Name: Offset: Reset: Property: DIRCLR 0x04 0x00000000 PAC Write-Protection This register allows the user to set one or more I/O pins as an input, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data Direction Set (DIRSET) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins.
PAGE 419
SAM D21 Family PORT - I/O Pin Controller 23.8.3 Data Direction Set Name: Offset: Reset: Property: DIRSET 0x08 0x00000000 PAC Write-Protection This register allows the user to set one or more I/O pins as an output, without doing a read-modify-write operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Toggle (DIRTGL) and Data Direction Clear (DIRCLR) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins.
PAGE 420
SAM D21 Family PORT - I/O Pin Controller 23.8.4 Data Direction Toggle Name: Offset: Reset: Property: DIRTGL 0x0C 0x00000000 PAC Write-Protection This register allows the user to toggle the direction of one or more I/O pins, without doing a read-modifywrite operation. Changes in this register will also be reflected in the Data Direction (DIR), Data Direction Set (DIRSET) and Data Direction Clear (DIRCLR) registers. Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins.
PAGE 421
SAM D21 Family PORT - I/O Pin Controller 23.8.5 Data Output Value Name: Offset: Reset: Property: OUT 0x10 0x00000000 PAC Write-Protection This register sets the data output drive value for the individual I/O pins in the PORT. This register can be manipulated without doing a read-modify-write operation by using the Data Output Value Clear (OUTCLR), Data Output Value Set (OUTSET), and Data Output Value Toggle (OUTTGL) registers.
PAGE 422
SAM D21 Family PORT - I/O Pin Controller Value 1 Description The I/O pin output is driven high, or the input is connected to an internal pull-up. © 2018 Microchip Technology Inc.
PAGE 423
SAM D21 Family PORT - I/O Pin Controller 23.8.6 Data Output Value Clear Name: Offset: Reset: Property: OUTCLR 0x14 0x00000000 PAC Write-Protection This register allows the user to set one or more output I/O pin drive levels low, without doing a readmodify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle (OUTTGL) and Data Output Value Set (OUTSET) registers.
PAGE 424
SAM D21 Family PORT - I/O Pin Controller Value 1 Description The corresponding I/O pin output is driven low, or the input is connected to an internal pulldown. © 2018 Microchip Technology Inc.
PAGE 425
SAM D21 Family PORT - I/O Pin Controller 23.8.7 Data Output Value Set Name: Offset: Reset: Property: OUTSET 0x18 0x00000000 PAC Write-Protection This register allows the user to set one or more output I/O pin drive levels high, without doing a readmodify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Toggle (OUTTGL) and Data Output Value Clear (OUTCLR) registers.
PAGE 426
SAM D21 Family PORT - I/O Pin Controller Value 1 Description The corresponding I/O pin output is driven high, or the input is connected to an internal pullup. © 2018 Microchip Technology Inc.
PAGE 427
SAM D21 Family PORT - I/O Pin Controller 23.8.8 Data Output Value Toggle Name: Offset: Reset: Property: OUTTGL 0x1C 0x00000000 PAC Write-Protection This register allows the user to toggle the drive level of one or more output I/O pins, without doing a readmodify-write operation. Changes in this register will also be reflected in the Data Output Value (OUT), Data Output Value Set (OUTSET) and Data Output Value Clear (OUTCLR) registers.
PAGE 428
SAM D21 Family PORT - I/O Pin Controller 23.8.9 Data Input Value Name: Offset: Reset: Property: IN 0x20 0x00000000 - Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing.
PAGE 429
SAM D21 Family PORT - I/O Pin Controller 23.8.10 Control Name: Offset: Reset: Property: CTRL 0x24 0x00000000 PAC Write-Protection Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing.
PAGE 430
SAM D21 Family PORT - I/O Pin Controller 23.8.11 Write Configuration Name: Offset: Reset: Property: WRCONFIG 0x28 0x00000000 PAC Write-Protection Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing.
PAGE 431
SAM D21 Family PORT - I/O Pin Controller Bit 30 – WRPINCFG Write PINCFG This bit determines whether the atomic write operation will update the Pin Configuration register (PINCFGy) or not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits. Writing '0' to this bit has no effect. Writing '1' to this bit updates the configuration of the selected pins with the written WRCONFIG.DRVSTR, WRCONFIG.PULLEN, WRCONFIG.INEN, WRCONFIG.PMUXEN, and WRCONFIG.PINMASK values.
PAGE 432
SAM D21 Family PORT - I/O Pin Controller Bit 16 – PMUXEN Peripheral Multiplexer Enable This bit determines the new value written to PINCFGy.PMUXEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set. This bit will always read as zero. Bits 15:0 – PINMASK[15:0] Pin Mask for Multiple Pin Configuration These bits select the pins to be configured within the half-word group selected by the WRCONFIG.HWSEL bit. These bits will always read as zero.
PAGE 433
SAM D21 Family PORT - I/O Pin Controller 23.8.12 Peripheral Multiplexing n Name: Offset: Reset: Property: PMUX 0x30 + n*0x01 [n=0..15] 0x00 PAC Write-Protection Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing.
PAGE 434
SAM D21 Family PORT - I/O Pin Controller Bits 3:0 – PMUXE[3:0] Peripheral Multiplexing for Even-Numbered Pin These bits select the peripheral function for even-numbered pins (2*n) of a PORT group, if the corresponding PINCFGy.PMUXEN bit is '1'. Not all possible values for this selection may be valid. For more details, refer to the I/O Multiplexing and Considerations.
PAGE 435
SAM D21 Family PORT - I/O Pin Controller 23.8.13 Pin Configuration Name: Offset: Reset: Property: PINCFG 0x40 + n*0x01 [n=0..31] 0x00 PAC Write-Protection Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing.
PAGE 436
SAM D21 Family PORT - I/O Pin Controller Bit 0 – PMUXEN Peripheral Multiplexer Enable This bit enables or disables the peripheral multiplexer selection set in the Peripheral Multiplexing register (PMUXn) to enable or disable alternative peripheral control over an I/O pin direction and output drive value. Writing a zero to this bit allows the PORT to control the pad direction via the Data Direction register (DIR) and output drive value via the Data Output Value register (OUT).
PAGE 437
SAM D21 Family EVSYS – Event System 24. EVSYS – Event System 24.1 Overview The Event System (EVSYS) allows autonomous, low-latency and configurable communication between peripherals. Several peripherals can be configured to generate and/or respond to signals known as events. The exact condition to generate an event, or the action taken upon receiving an event, is specific to each peripheral. Peripherals that respond to events are called event users.
PAGE 438
SAM D21 Family EVSYS – Event System 24.4 Signal Description Not applicable. 24.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 24.5.1 I/O Lines Not applicable. 24.5.2 Power Management The EVSYS can be used to wake up the CPU from all sleep modes, even if the clock used by the EVSYS channel and the EVSYS bus clock are disabled. Refer to the PM – Power Manager for details on the different sleep modes.
PAGE 439
SAM D21 Family EVSYS – Event System 24.5.8 Register Access Protection Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following: • Interrupt Flag Status and Clear register (INTFLAG) Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger. 24.5.9 Analog Connections Not applicable. 24.
PAGE 440
SAM D21 Family EVSYS – Event System To configure a user multiplexer, the USER register must be written in a single 16-bit write. It is possible to read out the configuration of a user by first selecting the user by writing to USER.USER using an 8-bit write and then performing a read of the 16-bit USER register. Figure 24-2. User MUX CHANNEL_EVT_0 CHANNEL_EVT_1 CHANNEL_EVT_m USER MUX USER.CHANNEL USER_EVT_x USER_EVT_y PERIPHERAL A USER_EVT_z PERIPHERAL B 24.6.2.
PAGE 441
SAM D21 Family EVSYS – Event System Figure 24-3. Channel The path is selected by writing to the Path Selection bit group in the Channel register (CHANNEL.PATH). 24.6.2.5.1 Asynchronous Path When using the asynchronous path, the events are propagated from the event generator to the event user without intervention from the Event System. The GCLK for this channel (GCLK_EVSYS_CHANNEL_n) is not mandatory, meaning that an event will be propagated to the user without any clock latency.
PAGE 442
SAM D21 Family EVSYS – Event System 24.6.2.5.3 Resynchronized Path The resynchronized path should be used when the event generator and the event channel do not share the same generic clock generator. When the resynchronized path is used, resynchronization of the event from the event generator is done in the channel. For details on generic clock generators, refer to GCLK Generic Clock Controller. When the resynchronized path is used, the channel is able to generate interrupts.
PAGE 443
SAM D21 Family EVSYS – Event System 24.6.3 Interrupts The EVSYS has the following interrupt sources: • • Overrun Channel n (OVRn): for details, refer to The Overrun Channel n Interrupt section. Event Detected Channel n (EVDn): for details, refer to The Event Detected Channel n Interrupt section. These interrupts events are asynchronous wake-up sources. See Sleep Mode Controller. Each interrupt source has an interrupt flag which is in the Interrupt Flag Status and Clear (INTFLAG) register.
PAGE 444
SAM D21 Family EVSYS – Event System Some event generators can generate an event when the system clock is stopped. The generic clock (GCLK_EVSYS_CHANNELx) for this channel will be restarted if the channel uses a synchronized path or a resynchronized path, without waking the system from sleep. The clock remains active only as long as necessary to handle the event. After the event has been handled, the clock will be turned off and the system will remain in the original sleep mode.
PAGE 445
SAM D21 Family EVSYS – Event System 24.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Refer to 24.
PAGE 446
SAM D21 Family EVSYS – Event System 24.8.1 Control Name: Offset: Reset: Property: Bit 7 CTRL 0x00 0x00 Write-Protected 6 5 Access Reset 4 3 2 1 0 GCLKREQ SWRST R/W W 0 0 Bit 4 – GCLKREQ Generic Clock Requests This bit is used to determine whether the generic clocks used for the different channels should be on all the time or only when an event needs the generic clock. Events propagated through asynchronous paths will not need a generic clock.
PAGE 447
SAM D21 Family EVSYS – Event System 24.8.
PAGE 448
SAM D21 Family EVSYS – Event System PATH[1:0] Name Description 0x0 SYNCHRONOUS Synchronous path 0x1 RESYNCHRONIZED Resynchronized path 0x2 ASYNCHRONOUS Asynchronous path 0x3 Reserved Bits 22:16 – EVGEN[6:0] Event Generator Selection These bits are used to choose which event generator to connect to the selected channel.
PAGE 449
SAM D21 Family EVSYS – Event System ...........
PAGE 450
SAM D21 Family EVSYS – Event System ...........
PAGE 451
SAM D21 Family EVSYS – Event System Bit 8 – SWEVT Software Event This bit is used to insert a software event on the channel selected by the CHANNEL.CHANNEL bit group. This bit has the same behavior similar to an event. This bit must be written together with CHANNEL.CHANNEL using a 16-bit write. Writing a zero to this bit has no effect. Writing a one to this bit will trigger a software event for the corresponding channel. This bit will always return zero when read.
PAGE 452
SAM D21 Family EVSYS – Event System 24.8.3 User Multiplexer Name: Offset: Reset: Property: Bit USER 0x08 0x0000 Write-Protected 15 14 13 12 11 10 9 8 CHANNEL[4:0] Access R/W R/W R/W R/W R/W 0 0 0 0 0 3 2 1 0 Reset Bit 7 6 5 4 USER[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Reset Bits 12:8 – CHANNEL[4:0] Channel Event Selection These bits are used to select the channel to connect to the event user.
PAGE 453
SAM D21 Family EVSYS – Event System ...........
PAGE 454
SAM D21 Family EVSYS – Event System ...........
PAGE 455
SAM D21 Family EVSYS – Event System 24.8.
PAGE 456
SAM D21 Family EVSYS – Event System 24.8.
PAGE 457
SAM D21 Family EVSYS – Event System 24.8.
PAGE 458
SAM D21 Family EVSYS – Event System 24.8.
PAGE 459
SAM D21 Family SERCOM – Serial Communication Interface 25. SERCOM – Serial Communication Interface 25.1 Overview There are up to six instances of the serial communication interface (SERCOM) peripheral. A SERCOM can be configured to support a number of modes: I2C, SPI, and USART. When an instance of SERCOM is configured and enabled, all of the resources of that SERCOM instance will be dedicated to the selected mode.
PAGE 460
SAM D21 Family SERCOM – Serial Communication Interface 25.3 Block Diagram Figure 25-1. SERCOM Block Diagram SERCOM Register Interface CONTROL/STATUS Mode Specific TX/RX DATA BAUD/ADDR Serial Engine Mode n Mode 1 Transmitter Baud Rate Generator Mode 0 Receiver 25.4 PAD[3:0] Address Match Signal Description See the respective SERCOM mode chapters for details. Related Links 26. SERCOM USART 27. SERCOM SPI – SERCOM Serial Peripheral Interface 28. SERCOM I2C – Inter-Integrated Circuit 25.
PAGE 461
SAM D21 Family SERCOM – Serial Communication Interface Related Links 16. PM – Power Manager 25.5.3 Clocks The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Power Manager. Refer to Peripheral Clock Masking for details and default status of this clock. The SERCOM uses two generic clocks: GCLK_SERCOMx_CORE and GCLK_SERCOMx_SLOW. The core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while working as a master.
PAGE 462
SAM D21 Family SERCOM – Serial Communication Interface • • Data register (DATA) Address register (ADDR) Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger. Related Links 11.6 PAC - Peripheral Access Controller 25.5.9 Analog Connections Not applicable. 25.6 Functional Description 25.6.
PAGE 463
SAM D21 Family SERCOM – Serial Communication Interface 25.6.2 Basic Operation 25.6.2.1 Initialization The SERCOM must be configured to the desired mode by writing the Operating Mode bits in the Control A register (CTRLA.MODE). Refer to table SERCOM Modes for details. Table 25-1. SERCOM Modes CTRLA.
PAGE 464
SAM D21 Family SERCOM – Serial Communication Interface Figure 25-3. Baud Rate Generator Selectable Internal Clk (GCLK) Baud Rate Generator 1 Ext Clk fref 0 Base Period /2 /1 CTRLA.MODE[0] /8 /2 /16 0 Tx Clk 1 1 CTRLA.MODE 0 1 Clock Recovery Rx Clk 0 Table 25-2 contains equations for the baud rate (in bits per second) and the BAUD register value for each operating mode. For asynchronous operation, the BAUD register value is 16 bits (0 to 65,535).
PAGE 465
SAM D21 Family SERCOM – Serial Communication Interface Table 25-3. BAUD Register Value vs. Baud Frequency 25.6.3 BAUD Register Value Serial Engine CPF fBAUD at 48MHz Serial Engine Frequency (fREF) 0 – 406 160 3MHz 407 – 808 161 2.981MHz 809 – 1205 162 2.963MHz ... ... ... 65206 31775 15.11kHz 65207 31871 15.06kHz 65208 31969 15.01kHz Additional Features 25.6.3.
PAGE 466
SAM D21 Family SERCOM – Serial Communication Interface 25.6.3.1.3 Address Range The range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK will cause a match. ADDR.ADDR and ADDR.ADDRMASK can be set to any two addresses, with ADDR.ADDR acting as the upper limit and ADDR.ADDRMASK acting as the lower limit. Figure 25-6. Address Range ADDRMASK 25.6.4 rx shift register ADDR == Match DMA Operation The available DMA interrupts and their depend on the operation mode of the SERCOM peripheral.
PAGE 467
SAM D21 Family SERCOM – Serial Communication Interface Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Required read-synchronization is denoted by the "Read-Synchronized" property in the register description. Related Links 14.3 Register Synchronization © 2018 Microchip Technology Inc.
PAGE 468
SAM D21 Family SERCOM USART 26. SERCOM USART 26.1 Overview The Universal Synchronous and Asynchronous Receiver and Transmitter (USART) is one of the available modes in the Serial Communication Interface (SERCOM). The USART uses the SERCOM transmitter and receiver, see 26.3 Block Diagram. Labels in uppercase letters are synchronous to CLK_SERCOMx_APB and accessible for CPU. Labels in lowercase letters can be programmed to run on the internal generic clock or an external clock.
PAGE 469
SAM D21 Family SERCOM USART 26.3 Block Diagram Figure 26-1. USART Block Diagram BAUD GCLK (internal) TX DATA Baud Rate Generator /1 - /2 - /16 CTRLA.MODE TX Shift Register TxD RX Shift Register RxD XCK CTRLA.MODE 26.4 Status RX Buffer STATUS RX DATA Signal Description Table 26-1. SERCOM USART Signals Signal Name Type Description PAD[3:0] Digital I/O General SERCOM pins One signal can be mapped to one of several pins. Related Links 7. I/O Multiplexing and Considerations 26.
PAGE 470
SAM D21 Family SERCOM USART The combined configuration of PORT and the Transmit Data Pinout and Receive Data Pinout bit fields in the Control A register (CTRLA.TXPO and CTRLA.RXPO, respectively) will define the physical position of the USART signals in Table 26-2. Related Links 23. PORT - I/O Pin Controller 26.5.2 Power Management This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake up the device from sleep modes. Related Links 16.
PAGE 471
SAM D21 Family SERCOM USART data loss may result during debugging. This peripheral can be forced to halt operation during debugging refer to the Debug Control (DBGCTRL) register for details. Related Links 26.8.11 DBGCTRL 26.5.8 Register Access Protection Registers with write-access can be write-protected optionally by the peripheral access controller (PAC).
PAGE 472
SAM D21 Family SERCOM USART St Start bit. Signal is always low. n, [n] [P] Data bits. 0 to [5..9] Parity bit. Either odd or even. Sp, [Sp] Stop bit. Signal is always high. IDLE No frame is transferred on the communication line. Signal is always high in this state. 26.6.2 Basic Operation 26.6.2.1 Initialization The following registers are enable-protected, meaning they can only be written when the USART is disabled (CTRL.
PAGE 473
SAM D21 Family SERCOM USART 26.6.2.2 Enabling, Disabling, and Resetting This peripheral is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE), and disabled by writing '0' to it. Writing ‘1’ to the Software Reset bit in the Control A register (CTRLA.SWRST) will reset all registers of this peripheral to their initial states, except the DBGCTRL register, and the peripheral is disabled. Refer to the CTRLA register description for details. 26.6.2.
PAGE 474
SAM D21 Family SERCOM USART When CTRLA.CPOL is '1', the data will be changed on the falling edge of XCK, and sampled on the rising edge of XCK. Figure 26-4. Synchronous Mode XCK Timing Change XCK CTRLA.CPOL=1 RxD / TxD Change Sample XCK CTRLA.CPOL=0 RxD / TxD Sample When the clock is provided through XCK (CTRLA.MODE=0x0), the shift registers operate directly on the XCK clock.
PAGE 475
SAM D21 Family SERCOM USART The received data can be read from the DATA register when the Receive Complete interrupt flag is set. 26.6.2.6.1 Disabling the Receiver Writing '0' to the Receiver Enable bit in the CTRLB register (CTRLB.RXEN) will disable the receiver, flush the two-level receive buffer, and data from ongoing receptions will be lost. 26.6.2.6.
PAGE 476
SAM D21 Family SERCOM USART ...........continued D RSLOW [%] RFAST [%] Max. total error [%] Recommended max. Rx error [%] (Data bits+Parity) 9 96.39 104.76 +3.61/-4.76 ±1.5 10 96.70 104.35 +3.30/-4.35 ±1.
PAGE 477
SAM D21 Family SERCOM USART Related Links 25.6.2.3 Clock Generation – Baud-Rate Generator 25.6.2.3.1 Asynchronous Arithmetic Mode BAUD Value Selection 26.6.3 Additional Features 26.6.3.1 Parity Even or odd parity can be selected for error checking by writing 0x1 to the Frame Format bit field in the Control A register (CTRLA.FORM). If even parity is selected (CTRLB.
PAGE 478
SAM D21 Family SERCOM USART Figure 26-9. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 26.6.3.3 IrDA Modulation and Demodulation Transmission and reception can be encoded IrDA compliant up to 115.2 kb/s. IrDA modulation and demodulation work in the following configuration: • • • IrDA encoding enabled (CTRLB.ENC=1), Asynchronous mode (CTRLA.CMODE=0), and 16x sample rate (CTRLA.SAMPR[0]=0). During transmission, each low bit is transmitted as a high pulse.
PAGE 479
SAM D21 Family SERCOM USART • and 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). The USART uses a break detection threshold of greater than 11 nominal bit times at the configured baud rate. At any time, if more than 11 consecutive dominant bits are detected on the bus, the USART detects a Break Field. When a Break Field has been detected, the Receive Break interrupt flag (INTFLAG.RXBRK) is set and the USART expects the Sync Field character to be 0x55.
PAGE 480
SAM D21 Family SERCOM USART 2. 3. 4. 5. Flush the transmit buffer. Disable transmitter (CTRLB.TXEN=0) – This is done after a synchronization delay. The CTRLB Synchronization Busy bit (SYNCBUSY.CTRLB) will be set until this is complete. – After disabling, the TxD pin will be tri-stated. Set the Collision Detected bit (STATUS.COLL) along with the Error interrupt flag (INTFLAG.ERROR). Set the Transmit Complete interrupt flag (INTFLAG.TXC), since the transmit buffer no longer contains data.
PAGE 481
SAM D21 Family SERCOM USART pointer (USARTRDPTR). All of these pointers reset to ‘0’. The CPUWRPTR and CPURDPTR pointers are native to the CPU clock domain, while the USARTWRPTR and USARTRDPTR are native to the USART domain. The location pointed to by the CPUWRPTR is the current TX FIFO. The location pointed to by the CPURDPTR becomes the current RX FIFO. Writes to DATA register by the CPU will point to TX FIFO. Reads to DATA register by the CPU will point to RX FIFO.
PAGE 482
SAM D21 Family SERCOM USART Depending the TX FIFO Threshold settings (CTRLC.TXTRHOLD), Interrupt Flag Status and Clear register (INTFLAG.DRE) indicates that the register is empty and ready for new data. DATA to TX FIFO should only be written to when INTFLAG.DRE is set. If the USART is halted when debugging, the CPUWRPTR pointer can be accessed by writting the CPUWRPTR bits in FIFOPTR register (FIFOPTR.CPUWRPTR). These bits will not increment if a new data is written into the TX FIFO memory. 26.6.3.9.
PAGE 483
SAM D21 Family SERCOM USART Table 26-5.
PAGE 484
SAM D21 Family SERCOM USART Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the interrupt condition is met. Each interrupt can be individually enabled by writing '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR).
PAGE 485
SAM D21 Family SERCOM USART 26.7 Offset Register Summary Name Bit Pos. 7:0 0x00 0x04 CTRLA CTRLB RUNSTDBY 15:8 MODE[2:0] ENABLE SAMPR[2:0] 23:16 SAMPA[1:0] 31:24 DORD 7:0 SBMODE 15:8 IBON RXPO[1:0] CPOL TXPO[1:0] CMODE FORM[3:0] CHSIZE[2:0] PMODE 23:16 SWRST ENC FIFOCLR[1:0] SFDE COLDEN RXEN TXEN 31:24 0x08 ... Reserved 0x0B 0x0C BAUD 0x0E RXPL 7:0 BAUD[7:0] 15:8 BAUD[15:8] 7:0 RXPL[7:0] 0x0F ...
PAGE 486
SAM D21 Family SERCOM USART ...........continued Offset Name 0x36 FIFOPTR 26.8 Bit Pos. 7:0 CPUWRPTR[3:0] 15:8 CPURDPTR[3:0] Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written.
PAGE 487
SAM D21 Family SERCOM USART 26.8.
PAGE 488
SAM D21 Family SERCOM USART This bit is not synchronized. Value 0 1 Description Asynchronous communication. Synchronous communication. Bits 27:24 – FORM[3:0] Frame Format These bits define the frame format. These bits are not synchronized. FORM[3:0] Description 0x0 USART frame 0x1 USART frame with parity 0x2-0x3 Reserved 0x4 Auto-baud - break detection and auto-baud.
PAGE 489
SAM D21 Family SERCOM USART This bit is not synchronized. TXPO TxD Pin Location XCK Pin Location (When Applicable) RTS CTS 0x0 SERCOM PAD[0] SERCOM PAD[1] N/A N/A 0x1 SERCOM PAD[2] SERCOM PAD[3] N/A N/A 0x2 SERCOM PAD[0] N/A SERCOM PAD[2] SERCOM PAD[3] 0x3 Reserved Bits 15:13 – SAMPR[2:0] Sample Rate These bits select the sample rate. These bits are not synchronized. SAMPR[2:0] Description 0x0 16x over-sampling using arithmetic baud rate generation.
PAGE 490
SAM D21 Family SERCOM USART Bits 4:2 – MODE[2:0] Operating Mode These bits select the USART serial communication interface of the SERCOM. These bits are not synchronized. Value 0x0 0x1 Description USART with external clock USART with internal clock Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/ disabled. The value written to CTRLA.
PAGE 491
SAM D21 Family SERCOM USART 26.8.
PAGE 492
SAM D21 Family SERCOM USART Writing '1' to CTRLB.RXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set until the receiver is enabled, and CTRLB.RXEN will read back as '1'. This bit is not enable-protected. Value 0 1 Description The receiver is disabled or being enabled. The receiver is enabled or will be enabled when the USART is enabled. Bit 16 – TXEN Transmitter Enable Writing '0' to this bit will disable the USART transmitter.
PAGE 493
SAM D21 Family SERCOM USART SFDE INTENSET.RXS INTENSET.RXC Description 0 X X Start-of-frame detection disabled. 1 0 0 Reserved 1 0 1 Start-of-frame detection enabled. RXC wakes up the device from all sleep modes. 1 1 0 Start-of-frame detection enabled. RXS wakes up the device from all sleep modes. 1 1 1 Start-of-frame detection enabled. Both RXC and RXS wake up the device from all sleep modes. Bit 8 – COLDEN Collision Detection Enable This bit enables collision detection.
PAGE 494
SAM D21 Family SERCOM USART 26.8.3 Baud Name: Offset: Reset: Property: Bit 15 BAUD 0x0C 0x0000 Enable-Protected, PAC Write-Protection 14 13 12 11 10 9 8 BAUD[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BAUD[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 – BAUD[15:0] Baud Value Arithmetic Baud Rate Generation (CTRLA.
PAGE 495
SAM D21 Family SERCOM USART 26.8.4 Receive Pulse Length Register Name: Offset: Reset: Property: Bit 7 RXPL 0x0E 0x00 Enable-Protected, PAC Write-Protection 6 5 4 3 2 1 0 RXPL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – RXPL[7:0] Receive Pulse Length When the encoding format is set to IrDA (CTRLB.
PAGE 496
SAM D21 Family SERCOM USART 26.8.5 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x14 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
PAGE 497
SAM D21 Family SERCOM USART Bit 2 – RXC Receive Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Receive Complete Interrupt Enable bit, which disables the Receive Complete interrupt. Value 0 1 Description Receive Complete interrupt is disabled. Receive Complete interrupt is enabled. Bit 1 – TXC Transmit Complete Interrupt Enable Writing '0' to this bit has no effect.
PAGE 498
SAM D21 Family SERCOM USART 26.8.6 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x16 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
PAGE 499
SAM D21 Family SERCOM USART Bit 2 – RXC Receive Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete interrupt. Value 0 1 Description Receive Complete interrupt is disabled. Receive Complete interrupt is enabled. Bit 1 – TXC Transmit Complete Interrupt Enable Writing '0' to this bit has no effect.
PAGE 500
SAM D21 Family SERCOM USART 26.8.7 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit Access Reset 7 INTFLAG 0x18 0x00 - 5 4 3 2 1 0 ERROR 6 RXBRK CTSIC RXS RXC TXC DRE R/W R/W R/W R/W R R/W R 0 0 0 0 0 0 0 Bit 7 – ERROR Error This flag is cleared by writing '1' to it. This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register.
PAGE 501
SAM D21 Family SERCOM USART Writing '1' to this bit has no effect. Bit 1 – TXC Transmit Complete This flag is cleared by writing '1' to it or by writing new data to DATA. This flag is set when the entire frame in the transmit shift register has been shifted out and there are no new data in DATA. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the flag. Bit 0 – DRE Data Register Empty This flag is cleared by writing new data to DATA.
PAGE 502
SAM D21 Family SERCOM USART 26.8.8 Status Name: Offset: Reset: Property: Bit 15 STATUS 0x1A 0x0000 - 14 13 12 11 10 9 8 Access Reset Bit Access Reset 7 6 5 4 3 2 1 0 TXE COLL ISF CTS BUFOVF FERR PERR R/W R/W R/W R R/W R/W R/W 0 0 0 0 0 0 0 Bit 6 – TXE Transmitter Empty This bit will always read back as zero. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it.
PAGE 503
SAM D21 Family SERCOM USART This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when a buffer overflow condition is detected. A buffer overflow occurs when the receive buffer is full, there is a new character waiting in the receive shift register and a new start bit is detected. Writing '0' to this bit has no effect. Writing '1' to this bit will clear it.
PAGE 504
SAM D21 Family SERCOM USART 26.8.9 Synchronization Busy Name: Offset: Reset: Property: Bit SYNCBUSY 0x1C 0x00000000 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit CTRLB ENABLE SWRST Access R R R Reset 0 0 0 Bit 2 – CTRLB CTRLB Synchronization Busy Writing to the CTRLB register when the SERCOM is enabled requires synchronization. When writing to CTRLB the SYNCBUSY.
PAGE 505
SAM D21 Family SERCOM USART Value 0 1 Description SWRST synchronization is not busy. SWRST synchronization is busy. © 2018 Microchip Technology Inc.
PAGE 506
SAM D21 Family SERCOM USART 26.8.10 Data Name: Offset: Reset: Property: Bit 15 DATA 0x28 0x0000 - 14 13 12 11 10 9 8 DATA[8:8] Access R/W Reset Bit 0 7 6 5 4 3 2 1 0 DATA[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 8:0 – DATA[8:0] Data Reading these bits will return the contents of the Receive Data register. The register should be read only when the Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.
PAGE 507
SAM D21 Family SERCOM USART 26.8.11 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x30 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGSTOP Access R/W Reset 0 Bit 0 – DBGSTOP Debug Stop Mode This bit controls the baud-rate generator functionality when the CPU is halted by an external debugger. Value 0 1 Description The baud-rate generator continues normal operation when the CPU is halted by an external debugger.
PAGE 508
SAM D21 Family SERCOM USART 26.8.12 FIFO Space Name: Offset: Reset: Property: FIFOSPACE 0x34 0x0000 - This register allows the user to identify the number of bytes present in each TX and RX FIFO.
PAGE 509
SAM D21 Family SERCOM USART 26.8.13 FIFO CPU Pointers Name: Offset: Reset: Property: FIFOPTR 0x36 0x0000 - This register provides a copy of internal CPU TX and RX FIFO pointers. Bit 15 14 13 12 11 10 9 8 CPURDPTR[3:0] Access Reset Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 CPUWRPTR[3:0] Access Reset Bits 11:8 – CPURDPTR[3:0] RX FIFO Filled Space These bits return the CPURDPTR pointer value.
PAGE 510
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27. 27.1 SERCOM SPI – SERCOM Serial Peripheral Interface Overview The serial peripheral interface (SPI) is one of the available modes in the Serial Communication Interface (SERCOM). The SPI uses the SERCOM transmitter and receiver configured as shown in 27.3 Block Diagram. Each side, master and slave, depicts a separate SPI containing a shift register, a transmit buffer and a two-level receive buffer.
PAGE 511
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.3 Block Diagram Figure 27-1. Full-Duplex SPI Master Slave Interconnection Master BAUD Slave Tx DATA Tx DATA ADDR/ADDRMASK SCK _SS baud rate generator shift register MISO shift register MOSI 27.4 rx buffer rx buffer Rx DATA Rx DATA == Address Match Signal Description Table 27-1. SERCOM SPI Signals Signal Name Type Description PAD[3:0] Digital I/O General SERCOM pins One signal can be mapped to one of several pins.
PAGE 512
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface The combined configuration of PORT, the Data In Pinout and the Data Out Pinout bit groups in the Control A register (CTRLA.DIPO and CTRLA.DOPO) define the physical position of the SPI signals in the table above. Related Links 23. PORT - I/O Pin Controller 27.5.2 Power Management This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake up the device from sleep modes. Related Links 16.
PAGE 513
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.5.8 Register Access Protection Registers with write-access can be write-protected optionally by the peripheral access controller (PAC). PAC Write-Protection is not available for the following registers: • • • Interrupt Flag Clear and Status register (INTFLAG) Status register (STATUS) Data register (DATA) Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register description.
PAGE 514
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.6.2 Basic Operation 27.6.2.1 Initialization The following registers are enable-protected, meaning that they can only be written when the SPI is disabled (CTRL.ENABLE=0): • • • • Control A register (CTRLA), except Enable (CTRLA.ENABLE) and Software Reset (CTRLA.SWRST) Control B register (CTRLB), except Receiver Enable (CTRLB.RXEN) Baud register (BAUD) Address register (ADDR) When the SPI is enabled or is being enabled (CTRLA.
PAGE 515
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface In SPI slave operation (CTRLA.MODE is 0x2), the clock is provided by an external master on the SCK pin. This clock is used to directly clock the SPI shift register. Related Links 25.6.2.3 Clock Generation – Baud-Rate Generator 25.6.2.3.1 Asynchronous Arithmetic Mode BAUD Value Selection 27.6.2.
PAGE 516
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface Figure 27-3.
PAGE 517
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface transferred to the two-level receive buffer. The transfer takes place in the same clock cycle as the last data bit is shifted in. And the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set. The received data can be retrieved by reading DATA.
PAGE 518
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.6.3 Additional Features 27.6.3.1 Address Recognition When the SPI is configured for slave operation (CTRLA.MODE=0x2) with address recognition (CTRLA.FORM is 0x2), the SERCOM address recognition logic is enabled: the first character in a transaction is checked for an address match. If there is a match, the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.
PAGE 519
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.6.3.3 Master with Several Slaves Master with multiple slaves in parallel is only available when Master Slave Select Enable (CTRLB.MSSEN) is set to zero and hardware SS control is disabled. If the bus consists of several SPI slaves, an SPI master can use general purpose I/O pins to control the SS line to each of the slaves on the bus, as shown in Multiple Slaves in Parallel.
PAGE 520
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface In Hardware Controlled SS, the time T is between one and two baud cycles depending on the SPI transfer mode. Figure 27-7. Hardware Controlled SS T T T T T _SS SCK T = 1 to 2 baud cycles When CTRLB.MSSEN=0, the SS pin(s) is/are controlled by user software and normal GPIO. 27.6.3.6 Slave Select Low Detection In slave mode, the SPI can wake the CPU when the slave select (SS) goes low. When the Slave Select Low Detect is enabled (CTRLB.
PAGE 521
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface The interrupts and DMA triggers are generated according to FIFO threshold settings in Control C register (CTRLC.TXTRHOLD, CTRLC.RXTRHOLD). The Data Register Empty interrupt flag, and the DMA TX trigger respectivly, are generated when the available place in the TX FIFO is equal or higher than the threshold value defined by the CTRLC.TXTRHOLD settings.
PAGE 522
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.6.4 DMA, Interrupts, and Events Table 27-4. Module Request for SERCOM SPI Condition Request DMA Interrupt Event Data Register Empty (DRE) Yes (request cleared when data is written) Yes NA Receive Complete (RXC) Yes (request cleared when data is read) Yes Transmit Complete (TXC) NA Yes Slave Select low (SSL) NA Yes Error (ERROR) NA Yes Table 27-5.
PAGE 523
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface • Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty or if at least TXTRHOLD data locations are empty in the TX FIFO, when FIFO operation is enabled. The request is cleared when DATA is written. 27.6.4.2 Interrupts The SPI has the following interrupt sources.
PAGE 524
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface • • Enable bit in the CTRLA register (CTRLA.ENABLE) Receiver Enable bit in the CTRLB register (CTRLB.RXEN) Note: CTRLB.RXEN is write-synchronized somewhat differently. See also CTRLB register for details. Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Related Links 14.3 Register Synchronization © 2018 Microchip Technology Inc.
PAGE 525
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.7 Offset Register Summary Name Bit Pos. 7:0 0x00 0x04 CTRLA CTRLB RUNSTDBY MODE[2:0] ENABLE 15:8 SWRST IBON 23:16 DIPO[1:0] 31:24 DORD 7:0 PLOADEN 15:8 AMODE[1:0] 23:16 FIFOCLR[1:0] CPOL DOPO[1:0] CPHA FORM[3:0] CHSIZE[2:0] MSSEN SSDE RXEN 31:24 0x08 ... Reserved 0x0B 0x0C BAUD 7:0 BAUD[7:0] 0x0D ...
PAGE 526
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface ...........continued Offset Name 0x34 FIFOSPACE 0x36 FIFOPTR 27.8 Bit Pos. 7:0 TXSPACE[4:0] 15:8 RXSPACE[4:0] 7:0 CPUWRPTR[3:0] 15:8 CPURDPTR[3:0] Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
PAGE 527
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.8.
PAGE 528
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface This bit is not synchronized. Mode CPOL CPHA Leading Edge Trailing Edge 0x0 0 0 Rising, sample Falling, change 0x1 0 1 Rising, change Falling, sample 0x2 1 0 Falling, sample Rising, change 0x3 1 1 Falling, change Rising, sample Value 0 1 Description The data is sampled on a leading SCK edge and changed on a trailing SCK edge. The data is sampled on a trailing SCK edge and changed on a leading SCK edge.
PAGE 529
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface DOPO DO SCK Slave SS Master SS 0x0 PAD[0] PAD[1] PAD[2] System configuration 0x1 PAD[2] PAD[3] PAD[1] System configuration 0x2 PAD[3] PAD[1] PAD[2] System configuration 0x3 PAD[0] PAD[3] PAD[1] System configuration Bit 8 – IBON Immediate Buffer Overflow Notification This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is set when a buffer overflow occurs. This bit is not synchronized.
PAGE 530
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface Bit 0 – SWRST Software Reset Writing '0' to this bit has no effect. Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled. Writing ''1' to CTRL.SWRST will always take precedence, meaning that all other writes in the same writeoperation will be discarded. Any register write access during the ongoing reset will result in an APB error.
PAGE 531
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.8.
PAGE 532
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface Writing '1' to CTRLB.RXEN when the SPI is enabled will set SYNCBUSY.CTRLB, which will remain set until the receiver is enabled, and CTRLB.RXEN will read back as '1'. This bit is not enable-protected. Value 0 1 Description The receiver is disabled or being enabled. The receiver is enabled or it will be enabled when SPI is enabled. Bits 15:14 – AMODE[1:0] Address Mode These bits set the slave addressing mode when the frame format (CTRLA.
PAGE 533
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.8.3 Baud Rate Name: Offset: Reset: Property: Bit 7 BAUD 0x0C 0x00 PAC Write-Protection, Enable-Protected 6 5 4 3 2 1 0 BAUD[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – BAUD[7:0] Baud Register These bits control the clock generation, as described in the SERCOM Clock Generation – Baud-Rate Generator. Related Links 25.6.2.3 Clock Generation – Baud-Rate Generator 25.6.2.3.
PAGE 534
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.8.4 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x14 0x00 PAC Write-Protection This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
PAGE 535
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface Bit 0 – DRE Data Register Empty Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Data Register Empty Interrupt Enable bit, which disables the Data Register Empty interrupt. Value 0 1 Description Data Register Empty interrupt is disabled. Data Register Empty interrupt is enabled. © 2018 Microchip Technology Inc.
PAGE 536
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.8.5 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x16 0x00 PAC Write-Protection This register allows the user to disable an interrupt without read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
PAGE 537
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface Bit 0 – DRE Data Register Empty Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty interrupt. Value 0 1 Description Data Register Empty interrupt is disabled. Data Register Empty interrupt is enabled. © 2018 Microchip Technology Inc.
PAGE 538
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.8.6 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit Access Reset 7 INTFLAG 0x18 0x00 - 3 2 1 0 ERROR 6 5 4 SSL RXC TXC DRE R/W R/W R R/W R 0 0 0 0 0 Bit 7 – ERROR Error This flag is cleared by writing '1' to it. This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register. The BUFOVF error will set this interrupt flag.
PAGE 539
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface Bit 0 – DRE Data Register Empty This flag is cleared by writing new data to DATA. This flag is set when DATA is empty and ready for new data to transmit. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. © 2018 Microchip Technology Inc.
PAGE 540
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.8.7 Status Name: Offset: Reset: Property: Bit STATUS 0x1A 0x0000 – 15 14 13 12 11 7 6 5 4 3 10 9 8 2 1 0 Access Reset Bit BUFOVF Access R/W Reset 0 Bit 2 – BUFOVF Buffer Overflow Reading this bit before reading DATA will indicate the error status of the next character to be read. This bit is cleared by writing '1' to the bit or by disabling the receiver. This bit is set when a buffer overflow condition is detected.
PAGE 541
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.8.8 Synchronization Busy Name: Offset: Reset: Property: Bit SYNCBUSY 0x1C 0x00000000 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit CTRLB ENABLE SWRST Access R R R Reset 0 0 0 Bit 2 – CTRLB CTRLB Synchronization Busy Writing to the CTRLB when the SERCOM is enabled requires synchronization.
PAGE 542
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface Value 0 1 Description SWRST synchronization is not busy. SWRST synchronization is busy. © 2018 Microchip Technology Inc.
PAGE 543
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.8.
PAGE 544
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.8.10 Data Name: Offset: Reset: Property: Bit 15 DATA 0x28 0x0000 – 14 13 12 11 10 9 8 DATA[8:8] Access R/W Reset Bit 0 7 6 5 4 3 2 1 0 DATA[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 8:0 – DATA[8:0] Data Reading these bits will return the contents of the receive data buffer.
PAGE 545
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.8.11 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x30 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGSTOP Access R/W Reset 0 Bit 0 – DBGSTOP Debug Stop Mode This bit controls the functionality when the CPU is halted by an external debugger. Value 0 1 Description The baud-rate generator continues normal operation when the CPU is halted by an external debugger.
PAGE 546
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.8.12 FIFO Space Name: Offset: Reset: FIFOSPACE 0x34 0x0000 This register allows the user to identify the number of bytes present in each TX and RX FIFO.
PAGE 547
SAM D21 Family SERCOM SPI – SERCOM Serial Peripheral Interface 27.8.13 FIFO CPU Pointers Name: Offset: Reset: FIFOPTR 0x36 0x0000 This register provides a copy of internal CPU TX and RX FIFO pointers. Bit 15 14 13 12 11 10 9 8 CPURDPTR[3:0] Access Reset Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 CPUWRPTR[3:0] Access Reset R/W R/W R/W R/W 0 0 0 0 Bits 11:8 – CPURDPTR[3:0] RX FIFO Filled Space These bits return the CPURDPTR pointer value.
PAGE 548
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28. SERCOM I2C – Inter-Integrated Circuit 28.1 Overview The inter-integrated circuit ( I2C) interface is one of the available modes in the serial communication interface (SERCOM). The I2C interface uses the SERCOM transmitter and receiver configured as shown in Figure 28-1. Labels in capital letters are registers accessible by the CPU, while lowercase labels are internal to the SERCOM.
PAGE 549
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.3 Block Diagram Figure 28-1. I2C Single-Master Single-Slave Interconnection Master BAUD TxDATA TxDATA 0 baud rate generator Slave SCL SCL hold low 0 SCL hold low shift register shift register 0 SDA 0 RxDATA 28.
PAGE 550
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.5.2 Power Management This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake up the device from sleep modes. Related Links 16. PM – Power Manager 28.5.3 Clocks The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Power Manager. Refer to Peripheral Clock Masking for details and default status of this clock.
PAGE 551
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit PAC Write-Protection is not available for the following registers: • • • • Interrupt Flag Clear and Status register (INTFLAG) Status register (STATUS) Data register (DATA) Address register (ADDR) Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger. Related Links 11.6 PAC - Peripheral Access Controller 28.5.
PAGE 552
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Figure 28-2. Transaction Diagram Symbols Bus Driver Special Bus Conditions Master driving bus S START condition Slave driving bus Sr repeated START condition Either Master or Slave driving bus P STOP condition Data Package Direction Acknowledge Master Read R Acknowledge (ACK) A '0' '1' W A Master Write Not Acknowledge (NACK) '1' '0' Figure 28-3. Basic I2C Transaction Diagram SDA SCL 6..0 S ADDRESS S ADDRESS 7..
PAGE 553
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Enable-protection is denoted by the "Enable-Protection" property in the register description. Before the I2C is enabled it must be configured as outlined by the following steps: 1. Select I2C Master or Slave mode by writing 0x4 (Slave mode) or 0x5 (Master mode) to the Operating Mode bits in the CTRLA register (CTRLA.MODE). 2. If desired, select the SDA Hold Time value in the CTRLA register (CTRLA.SDAHOLD). 3.
PAGE 554
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Figure 28-4. Bus State Diagram RESET UNKNOWN (0b00) Timeout or Stop Condition Start Condition IDLE (0b01) Timeout or Stop Condition BUSY (0b11) Write ADDR to generate Start Condition OWNER (0b10) Lost Arbitration Repeated Start Condition Stop Condition Write ADDR to generate Repeated Start Condition The bus state machine is active when the I2C master is enabled. After the I2C master has been enabled, the bus state is UNKNOWN (0b00).
PAGE 555
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.6.2.4 I2C Master Operation The I2C master is byte-oriented and interrupt based. The number of interrupts generated is kept at a minimum by automatic handling of most incidents. The software driver complexity and code size are reduced by auto-triggering of operations, and a special smart mode, which can be enabled by the Smart Mode Enable bit in the Control A register (CTRLA.SMEN). The I2C master has two interrupt strategies.
PAGE 556
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Figure 28-6. I2C Master Behavioral Diagram (SCLSM=1) APPLICATION Master Bus INTERRUPT + SCL HOLD M1 M2 BUSY P M3 IDLE S M4 ADDRESS Wait for IDLE SW R/W BUSY SW R/W A SW P SW Sr W A M1 BUSY M2 IDLE M3 BUSY DATA SW A/A Slave Bus INTERRUPT + SCL HOLD SW Software interaction SW BUSY The master provides data on the bus P IDLE M4 M2 Addressed slave provides data on the bus Sr R A M3 DATA A/A 28.6.2.4.
PAGE 557
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Figure 28-7. SCL Timing TRISE P S Sr TLOW SCL THIGH TFALL TBUF SDA TSU;STO THD;STA TSU;STA The following parameters are timed using the SCL low time period TLOW. This comes from the Master Baud Rate Low bit group in the Baud Rate register (BAUD.BAUDLOW). When BAUD.BAUDLOW=0, or the Master Baud Rate bit group in the Baud Rate register (BAUD.BAUD) determines it.
PAGE 558
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Note: The I2C standard Fm+ (Fast-mode plus) requires a nominal high to low SCL ratio of 1:2, and BAUD should be set accordingly. At a minimum, BAUD.BAUD and/or BAUD.BAUDLOW must be nonzero. Startup Timing The minimum time between SDA transition and SCL rising edge is 6 APB cycles when the DATA register is written in smart mode.
PAGE 559
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit If there is no I2C slave device responding to the address packet, then the INTFLAG.MB interrupt flag and STATUS.RXNACK will be set. The clock hold is active at this point, preventing further activity on the bus. The missing ACK response can indicate that the I2C slave is busy with other tasks or sleeping. Therefore, it is not able to respond.
PAGE 560
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.6.2.4.4 Receiving Data Packets (SCLSM=0) When INTFLAG.SB is set, the I2C master will already have received one data packet. The I2C master must respond by sending either an ACK or NACK. Sending a NACK may be unsuccessful when arbitration is lost during the transmission. In this case, a lost arbitration will prevent setting INTFLAG.SB. Instead, INTFLAG.MB will indicate a change in arbitration.
PAGE 561
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Figure 28-9. 10-bit Address Transmission for a Read Transaction MB INTERRUPT 1 S 11110 addr[9:8] W A S W A addr[7:0] Sr 11110 addr[9:8] R A This implies the following procedure for a 10-bit read operation: 1. Write the 10-bit address to ADDR.ADDR[10:1]. ADDR.TENBITEN must be '1', the direction bit (ADDR.ADDR[0]) must be '0' (can be written simultaneously with ADDR). 2.
PAGE 562
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit In the second strategy (CTRLA.SCLSM=1), interrupts only occur after the ACK bit is sent as shown in Slave Behavioral Diagram (SCLSM=1). This strategy can be used when it is not necessary to check DATA before acknowledging. For master reads, an address and data interrupt will be issued simultaneously after the address acknowledge.
PAGE 563
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Case 1: Address packet accepted – Read flag set The STATUS.DIR bit is ‘1’, indicating an I2C master read operation. The SCL line is forced low, stretching the bus clock. If an ACK is sent, I2C slave hardware will set the Data Ready bit in the Interrupt Flag register (INTFLAG.DRDY), indicating data are needed for transmit. If a NACK is sent, the I2C slave will wait for a new start condition and address match.
PAGE 564
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit When a data packet is received or sent, INTFLAG.DRDY will be set. After receiving data, the I2C slave will send an acknowledge according to CTRLB.ACKACT. Case 1: Data received INTFLAG.DRDY is set, and SCL is held low, pending for SW interaction. Case 2: Data sent When a byte transmission is successfully completed, the INTFLAG.DRDY interrupt flag is set. If NACK is received, indicated by STATUS.
PAGE 565
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Figure 28-13. PMBus Group Command Example Command/Data S ADDRESS 0 W n Bytes A A AMATCH INTERRUPT DRDY INTERRUPT Command/Data Sr ADDRESS 1 (this slave) S W W A 28.6.3 ADDRESS 2 W A n Bytes A PREC INTERRUPT Command/Data Sr S W n Bytes A P S W Additional Features 28.6.3.
PAGE 566
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Figure 28-14. I2C Pad Interface SCL_OUT/ SDA_OUT SCL_OUT/ SDA_OUT pad PINOUT I2C Driver SCL/SDA pad SCL_IN/ SDA_IN PINOUT 28.6.3.4 Quick Command Setting the Quick Command Enable bit in the Control B register (CTRLB.QCEN) enables quick command. When quick command is enabled, the corresponding interrupt flag (INTFLAG.SB or INTFLAG.MB) is set immediately after the slave acknowledges the address.
PAGE 567
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit When using the I2C configured as Master, the Address register must be written with the desired address (ADDR.ADDR), and optionally, the transaction Length and transaction Length Enable bits (ADDR.LEN and ADDR.LENEN) can be written if the 32-bit extension is enabled (CTRLC.DATA32B). In slave operation, the Address Match interrupt in the Interrupt Flag Status and Clear register (INTFLAG.
PAGE 568
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Table 28-2. Bus Actions for Valid SERCOM I2C Master Configurations Direction CTRLB. CTRLC. LENGTH.
PAGE 569
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.6.3.5.2 Hardware Actions in Slave Mode Table 28-3. Interrupt Request Conditions for Valid SERCOM I2C Slave Configurations Direction CTRLB. CTRLC. LENGTH. Condition SMEN DATA32B LENEN Master Write 0 0 0 • INTFLAG.DRDY = 1 if RX FIFO is full 0 1 0 • INTFLAG.RXFF = 1 RX FIFO threshold is reached 0 1 1 1 0 0 1 1 0 1 1 1 Master Read 0 0 0 • 0 1 0 INTFLAG.DRDY = 1 if TX FIFO is empty and SCL hold INTFLAG.
PAGE 570
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Table 28-4. Bus Actions for Valid SERCOM I2C Slave Configurations Direction CTRLB. CTRLC. LENGTH. Actions SMEN DATA32B LENEN Master Write 0 0 0 • • Byte mode operation SCL stretched if RX FIFO is full 0 1 0 • • • 32-bit mode operation SCL stretched if RX FIFO is full ACK/NACK each 4th byte, depending on Acknowledge Action (CTRLB.
PAGE 571
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.6.4 DMA, Interrupts and Events This chapter provides DMA and interrupt conditions when the optional FIFO is disabled. For details when the FIFO is enabled, refer to FIFO Support. Each interrupt source has its own interrupt flag. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the interrupt condition is meet.
PAGE 572
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Table 28-6. Module Request for SERCOM I2C Master Condition Request DMA Interrupt Data needed for transmit (TX) (Master transmit mode) Yes (request cleared when data is written) Data needed for transmit (RX) (Master transmit mode) Yes (request cleared when data is read) Event NA Master on Bus (MB) Yes Stop received (SB) Yes TX FIFO Empty (TXFE) Yes RX FIFO Full (RXFF) Yes Error (ERROR) Yes 28.6.4.
PAGE 573
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit If a NACK is received by the slave for a master write transaction before ADDR.LEN bytes, a STOP will be automatically generated and the length error (STATUS.LENERR) will be raised along with the INTFLAG.ERROR interrupt. The I2C master generates the following requests: • • • • Read data received (RX): The request is set when master read data is received. The request is cleared when DATA is read.
PAGE 574
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.6.4.3 Events Not applicable. 28.6.5 Sleep Mode Operation I2C Master Operation The generic clock (GCLK_SERCOMx_CORE) will continue to run in idle sleep mode. If the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY) is '1', the GLK_SERCOMx_CORE will also run in standby sleep mode. Any interrupt can wake up the device. If CTRLA.RUNSTDBY=0, the GLK_SERCOMx_CORE will be disabled after any ongoing transaction is finished.
PAGE 575
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.7 Offset Register Summary - I2C Slave Name Bit Pos. 7:0 0x00 CTRLA RUNSTDBY MODE[2:0] ENABLE SWRST 15:8 23:16 SEXTTOEN 31:24 SDAHOLD[1:0] PINOUT LOWTOUT SCLSM SPEED[1:0] 7:0 0x04 CTRLB 15:8 AMODE[1:0] AACKEN 23:16 FIFOCLR[1:0] ACKACT GCMD SMEN CMD[1:0] 31:24 0x08 ...
PAGE 576
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.8 Register Description - I2C Slave Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC).
PAGE 577
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.8.
PAGE 578
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Value 0x0 0x1 0x2 0x3 Description Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz Fast-mode Plus (Fm+) up to 1 MHz High-speed mode (Hs-mode) up to 3.4 MHz Reserved Bit 23 – SEXTTOEN Slave SCL Low Extend Time-Out This bit enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine.
PAGE 579
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Bit 1 – ENABLE Enable Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/ disabled. The value written to CTRL.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not enable-protected.
PAGE 580
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.8.
PAGE 581
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Value 1 Description Send NACK Bits 17:16 – CMD[1:0] Command This bit field triggers the slave operation as the below. The CMD bits are strobe bits, and always read as zero. The operation is dependent on the slave interrupt flags, INTFLAG.DRDY and INTFLAG.AMATCH, in addition to STATUS.DIR. All interrupt flags (INTFLAG.DRDY, INTFLAG.AMATCH and INTFLAG.PREC) are automatically cleared when a command is given. This bit is not enable-protected. Table 28-7.
PAGE 582
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit This bit is not write-synchronized. Value 0 1 Description Automatic acknowledge is disabled. Automatic acknowledge is enabled. Bit 9 – GCMD PMBus Group Command This bit enables PMBus group command support. When enabled, the Stop Recived interrupt flag (INTFLAG.PREC) will be set when a STOP condition is detected if the slave has been addressed since the last STOP condition on the bus. This bit is not write-synchronized.
PAGE 583
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.8.3 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x14 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
PAGE 584
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Writing '1' to this bit will clear the Address Match Interrupt Enable bit, which disables the Address Match interrupt. Value 0 1 Description The Address Match interrupt is disabled. The Address Match interrupt is enabled. Bit 0 – PREC Stop Received Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Stop Received Interrupt Enable bit, which disables the Stop Received interrupt.
PAGE 585
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.8.4 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x16 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
PAGE 586
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Writing '1' to this bit will set the Address Match Interrupt Enable bit, which enables the Address Match interrupt. Value 0 1 Description The Address Match interrupt is disabled. The Address Match interrupt is enabled. Bit 0 – PREC Stop Received Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Stop Received Interrupt Enable bit, which enables the Stop Received interrupt.
PAGE 587
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.8.5 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 Access Reset INTFLAG 0x18 0x00 - 4 3 2 1 0 ERROR 6 5 RXFF TXFE DRDY AMATCH PREC R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bit 7 – ERROR Error This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STATUS register. The corresponding bits in STATUS are SEXTTOUT, LOWTOUT, COLL, and BUSERR.
PAGE 588
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit The flag is cleared by hardware when CTRL.CMD is written. Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Address Match interrupt flag. When cleared, an ACK/NACK will be sent according to CTRLB.ACKACT. Bit 0 – PREC Stop Received This flag is set when a stop condition is detected for a transaction being processed.
PAGE 589
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.8.6 Status Bit Name: Offset: Reset: STATUS 0x1A 0x0000 15 14 13 12 11 10 9 LENERR HS SEXTTOUT R/W R/W R/W 0 0 0 Access Reset Bit 5 8 7 6 4 3 2 1 0 CLKHOLD LOWTOUT SR DIR RXNACK COLL BUSERR Access R R/W R R R R/W R/W Reset 0 0 0 0 0 0 0 Bit 11 – LENERR Transaction Length Error This bit is set when the length counter is enabled (LENGTH.
PAGE 590
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit This bit is automatically cleared when the corresponding interrupt is also cleared. Bit 6 – LOWTOUT SCL Low Time-out This bit is set if an SCL low time-out occurs. This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD) or when INTFLAG.AMATCH is cleared. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the status. Value 0 1 Description No SCL low time-out has occurred.
PAGE 591
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Value 0 1 Description No collision detected on last data byte sent. Collision detected on last data byte sent. Bit 0 – BUSERR Bus Error The Bus Error bit (STATUS.BUSERR) indicates that an illegal bus condition has occurred on the bus, regardless of bus ownership. An illegal bus condition is detected if a protocol violating start, repeated start or stop is detected on the I2C bus lines.
PAGE 592
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.8.7 Synchronization Busy Name: Offset: Reset: Bit SYNCBUSY 0x1C 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 Access Reset Bit Access Reset Bit Access Reset Bit 2 1 0 SYSOP ENABLE SWRST Access R R R Reset 0 0 0 Bit 2 – SYSOP System Operation Synchronization Busy Writing CTRLB.FIFOCLR when the SERCOM is enabled requires synchronization.
PAGE 593
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.8.
PAGE 594
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Value 0 1 Description General call address recognition disabled. General call address recognition enabled. © 2018 Microchip Technology Inc.
PAGE 595
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.8.9 Data Name: Offset: Reset: Property: Bit DATA 0x28 0x0000 Write-Synchronized, Read-Synchronized 15 14 13 12 7 6 5 4 11 10 9 8 3 2 1 0 Access Reset Bit DATA[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – DATA[7:0] Data The slave data register I/O location (DATA.DATA) provides access to the master transmit and receive data buffers.
PAGE 596
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.8.10 FIFO Space Name: Offset: Reset: Property: FIFOSPACE 0x34 0x0000 - This register allows the user to identify the number of bytes present in each TX and RX FIFO.
PAGE 597
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.8.11 FIFO CPU Pointers Name: Offset: Reset: Property: FIFOPTR 0x36 0x0000 - This register provides a copy of internal CPU TX and RX FIFO pointers. Bit 15 14 13 12 11 10 9 8 CPURDPTR[3:0] Access Reset Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 CPUWRPTR[3:0] Access Reset Bits 11:8 – CPURDPTR[3:0] RX FIFO Filled Space These bits return the CPURDPTR pointer value.
PAGE 598
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.9 Offset Register Summary - I2C Master Name Bit Pos. 7:0 0x00 CTRLA RUNSTDBY MODE[2:0] ENABLE SWRST 15:8 23:16 SEXTTOEN 31:24 MEXTTOEN SDAHOLD[1:0] LOWTOUT INACTOUT[1:0] PINOUT SCLSM SPEED[1:0] 7:0 0x04 CTRLB 15:8 QCEN 23:16 FIFOCLR[1:0] ACKACT SMEN CMD[1:0] 31:24 0x08 ... Reserved 0x0B 0x0C BAUD 7:0 BAUD[7:0] 15:8 BAUDLOW[7:0] 23:16 HSBAUD[7:0] 31:24 HSBAUDLOW[7:0] 0x10 ...
PAGE 599
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit ...........continued Offset Name Bit Pos. 0x31 ... Reserved 0x33 0x34 FIFOSPACE 0x36 FIFOPTR 28.10 7:0 TXSPACE[4:0] 15:8 RXSPACE[4:0] 7:0 CPUWRPTR[3:0] 15:8 CPURDPTR[3:0] Register Description - I2C Master Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
PAGE 600
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.10.
PAGE 601
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Value 0x0 0x1 0x2 0x3 Name DIS 55US 105US 205US Description Disabled 5-6 SCL cycle time-out (50-60µs) 10-11 SCL cycle time-out (100-110µs) 20-21 SCL cycle time-out (200-210µs) Bit 27 – SCLSM SCL Clock Stretch Mode This bit controls when SCL will be stretched for software interaction. This bit is not synchronized. Value 0 1 Description SCL stretch according to Figure 28-5. SCL stretch only after ACK bit, Figure 28-6.
PAGE 602
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Bits 21:20 – SDAHOLD[1:0] SDA Hold Time These bits define the SDA hold time with respect to the negative edge of SCL. These bits are not synchronized. Value 0x0 0x1 0x2 0x3 Name DIS 75NS 450NS 600NS Description Disabled 50-100ns hold time 300-600ns hold time 400-800ns hold time Bit 16 – PINOUT Pin Usage This bit set the pin usage to either two- or four-wire operation: This bit is not synchronized. Value 0 1 Description 4-wire operation disabled.
PAGE 603
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.
PAGE 604
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.10.
PAGE 605
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Value 0 1 Description Send ACK. Send NACK. Bits 17:16 – CMD[1:0] Command Writing these bits triggers a master operation as described below. The CMD bits are strobe bits, and always read as zero. The acknowledge action is only valid in master read mode. In master write mode, a command will only result in a repeated start or stop condition. The CTRLB.
PAGE 606
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.10.
PAGE 607
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Bits 7:0 – BAUD[7:0] Master Baud Rate This bit field is used to derive the SCL high time if BAUD.BAUDLOW is non-zero. If BAUD.BAUDLOW is zero, BAUD will be used to generate both high and low periods of the SCL. For more information on how to calculate the frequency, see SERCOM 25.6.2.3 Clock Generation – Baud-Rate Generator. © 2018 Microchip Technology Inc.
PAGE 608
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.10.4 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x14 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
PAGE 609
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Bit 0 – MB Master on Bus Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the Master on Bus Interrupt Enable bit, which disables the Master on Bus interrupt. Value 0 1 Description The Master on Bus interrupt is disabled. The Master on Bus interrupt is enabled. © 2018 Microchip Technology Inc.
PAGE 610
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.10.5 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x16 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
PAGE 611
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Bit 0 – MB Master on Bus Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the Master on Bus Interrupt Enable bit, which enables the Master on Bus interrupt. Value 0 1 Description The Master on Bus interrupt is disabled. The Master on Bus interrupt is enabled. © 2018 Microchip Technology Inc.
PAGE 612
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.10.6 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 Access Reset INTFLAG 0x18 0x00 - 4 3 1 0 ERROR 6 5 RXFF TXFE 2 SB MB R/W R/W R/W R/W R/W 0 0 0 0 0 Bit 7 – ERROR Error This flag is cleared by writing '1' to it. This bit is set when any error is detected. Errors that will set this flag have corresponding status bits in the STATUS register.
PAGE 613
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Writing '0' to this bit has no effect. Bit 0 – MB Master on Bus This flag is set when a byte is transmitted in master write mode. The flag is set regardless of the occurrence of a bus error or an arbitration lost condition. MB is also set when arbitration is lost during sending of NACK in master read mode, or when issuing a start condition if the bus state is unknown.
PAGE 614
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.10.
PAGE 615
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit This bit is cleared when the corresponding interrupt flag is cleared and the next operation is given. Writing '0' to this bit has no effect. Writing '1' to this bit has no effect. This bit is not write-synchronized. Bit 6 – LOWTOUT SCL Low Time-Out This bit is set if an SCL low time-out occurs. Writing '1' to this bit location will clear this bit. This flag is automatically cleared when writing to the ADDR register. Writing '0' to this bit has no effect.
PAGE 616
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Bit 0 – BUSERR Bus Error This bit indicates that an illegal bus condition has occurred on the bus, regardless of bus ownership. An illegal bus condition is detected if a protocol violating start, repeated start or stop is detected on the I2C bus lines. A start condition directly followed by a stop condition is one example of a protocol violation. If a time-out occurs during a frame, this is also considered a protocol violation, and will set BUSERR.
PAGE 617
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.10.8 Synchronization Busy Name: Offset: Reset: Bit SYNCBUSY 0x1C 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 Access Reset Bit Access Reset Bit Access Reset Bit 2 1 0 SYSOP ENABLE SWRST Access R R R Reset 0 0 0 Bit 2 – SYSOP System Operation Synchronization Busy Writing CTRLB.CMD, STATUS.
PAGE 618
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Value 0 1 Description SWRST synchronization is not busy. SWRST synchronization is busy. © 2018 Microchip Technology Inc.
PAGE 619
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.10.
PAGE 620
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit Value 0 1 Description Automatic transfer length disabled. Automatic transfer length enabled. Bits 10:0 – ADDR[10:0] Address When ADDR is written, the consecutive operation will depend on the bus state: UNKNOWN: INTFLAG.MB and STATUS.BUSERR are set, and the operation is terminated. BUSY: The I2C master will await further operation until the bus becomes IDLE. IDLE: The I2C master will issue a start condition followed by the address written in ADDR.
PAGE 621
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.10.10 Data Name: Offset: Reset: Property: Bit DATA 0x28 0x0000 - 15 14 13 12 7 6 5 4 11 10 9 8 3 2 1 0 Access Reset Bit DATA[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – DATA[7:0] Data The master data register I/O location (DATA) provides access to the master transmit and receive data buffers.
PAGE 622
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.10.11 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x30 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGSTOP Access R/W Reset 0 Bit 0 – DBGSTOP Debug Stop Mode This bit controls functionality when the CPU is halted by an external debugger. Value 0 1 Description The baud-rate generator continues normal operation when the CPU is halted by an external debugger.
PAGE 623
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.10.12 FIFO Space Name: Offset: Reset: Property: FIFOSPACE 0x34 0x0000 - This register allows the user to identify the number of bytes present in each TX and RX FIFO.
PAGE 624
SAM D21 Family SERCOM I2C – Inter-Integrated Circuit 28.10.13 FIFO CPU Pointers Name: Offset: Reset: Property: FIFOPTR 0x36 0x0000 - This register provides a copy of internal CPU TX and RX FIFO pointers. Bit 15 14 13 12 11 10 9 8 CPURDPTR[3:0] Access Reset Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 CPUWRPTR[3:0] Access Reset Bits 11:8 – CPURDPTR[3:0] RX FIFO Filled Space These bits return the CPURDPTR pointer value.
PAGE 625
SAM D21 Family I2S - Inter-IC Sound Controller 29. I2S - Inter-IC Sound Controller 29.1 Overview The Inter-IC Sound Controller (I2S) provides bidirectional, synchronous and digital audio link with external audio devices. This controller is compliant with the Inter-IC Sound (I2S) bus specification. It supports TDM interface with external multi-slot audio codecs. It also supports PDM interface with external MEMS microphones.
PAGE 626
SAM D21 Family I2S - Inter-IC Sound Controller – • • • • 29.3 Suitable for a wide range of sample frequencies fs, including 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, and 192kHz – 16×fs to 1024×fs Master Clock generated for external audio CODECs Master, slave, and controller modes: – Master: Data received/transmitted based on internally-generated clocks.
PAGE 627
SAM D21 Family I2S - Inter-IC Sound Controller 29.4 Signal Description Table 29-1. Master Mode Pin Name Pin Description Type MCKn Master Clock for Clock Unit n Input/Output SCKn Serial Clock for Clock Unit n Input/Output FSn I2S Word Select or TDM Frame Sync for Clock Unit n Input/Output SDm Serial Data Input or Output for Serializer m Input/Output Table 29-2.
PAGE 628
SAM D21 Family I2S - Inter-IC Sound Controller 29.5.2 Power Management The I2S will continue to operate in any sleep mode where the selected source clocks are running. 29.5.3 Clocks The clock for the I2S bus interface (CLK_I2S_APB) is generated by the Power Manager. This clock is disabled at reset, and can be enabled in the Power Manager. It is recommended to disable the I2S before disabling the clock, to avoid freezing the I2S in an undefined state.
PAGE 629
SAM D21 Family I2S - Inter-IC Sound Controller Write-protection does not apply for accesses through an external debugger. 29.5.9 Analog Connections Not applicable. 29.6 Functional Description 29.6.1 Principle of Operation The I2S uses three or four communication lines for synchronous data transfer: • • • • SDm for receiving or transmitting in Serializer m (m=0..1) SCKn for the serial clock in Clock Unit n (n=0..
PAGE 630
SAM D21 Family I2S - Inter-IC Sound Controller In mono format, Transmit mode, data written to the left channel is duplicated to the right output channel. In mono format, Receiver mode, data received from the right channel is ignored and data received from the left channel is duplicated in to the right channel. In mono format, TDM Transmit mode with more than two slots, data written to the even-numbered slots is duplicated in to the following odd-numbered slot.
PAGE 631
SAM D21 Family I2S - Inter-IC Sound Controller Figure 29-3. I2S Functional Block Diagram 29.6.1.1 Initialization The I2S features two Clock Units, and two Serializers configurable as Receiver or Transmitter. The two Serializers can either share the same Clock Unit or use separate Clock Units.
PAGE 632
SAM D21 Family I2S - Inter-IC Sound Controller fSCKn = 48kHz × 6 × 32 = 9.216MHz This frequency can be achieved by dividing the I2S generic clock output of 18.432MHz by factor 2: Writing CLKCTRLn.MCKDIV=0x1 will select the correct division factor and output the desired SCKn frequency of 9.216MHz to the SCKn pin. If MCKn is not required, the generic clock could be set to 9.216MHz and CLKCTRLn.MCKDIV=0x0. 29.6.
PAGE 633
SAM D21 Family I2S - Inter-IC Sound Controller Figure 29-4. I2S Clocks Generation 29.6.2.1.1 Slave Mode In Slave mode, the Serial Clock and Frame Sync (Word Select in I2S mode and Frame Sync in TDM mode) are driven by an external master. SCKn and FSn pins are inputs and no generic clock is required by the I2S. 29.6.2.1.2 Master Mode and Controller Mode In Master Mode, the Master Clock (MCKn), the Serial Clock (SCKn), and the Frame Sync Clock (FSn) are generated by the I2S controller.
PAGE 634
SAM D21 Family I2S - Inter-IC Sound Controller In Controller mode, only the Clock generation unit needs to be configured by writing to the CTRLA and CLKCTRLn registers, where parameters such as clock division factors, Number of slots, Slot size, Frame Sync signal, clock enable are selected. 29.6.2.1.3 MCKn Clock Frequency When the I2S is in Master mode, writing a '1' to CLKCTRLn.MCKEN will output GCLK_I2S_n as Master Clock to the MCKn pin. The Master Clock to MCKn pin can be divided by writing to CLKCTRLn.
PAGE 635
SAM D21 Family I2S - Inter-IC Sound Controller The FSn pin is used as Word Select in I2S format and as Frame Synchronization in TDM format, as described in 29.6.4 I2S Format - Reception and Transmission Sequence with Word Select and 29.6.5 TDM Format - Reception and Transmission Sequence, respectively. 29.6.2.2 Data Holding Registers For each Serializer m, the I2S user interface includes a Data m register (DATAm). They are used to access data samples for all data slots. 29.6.2.2.
PAGE 636
SAM D21 Family I2S - Inter-IC Sound Controller Data bits are sent on the falling edge of the Serial Clock and sampled on the rising edge of the Serial Clock. The Word Select line indicates the channel in transmission, a low level for the left channel and a high level for the right channel. In I2S format, typical configurations are described below. These configurations do not list all necessary settings, but only basic ones.
PAGE 637
SAM D21 Family I2S - Inter-IC Sound Controller Data bits are sent on the falling edge of the Serial Clock and sampled on the rising edge of the Serial Clock. The FSn pin provides a frame synchronization signal, at the beginning of slot 0. The delay between the frame start and the first data bit is defined by writing the CLKCTRLn.BITDELAY field. The Frame Sync pulse can be either one SCKn period (BIT), one slot (SLOT), or one half frame (HALF). This selection is done by writing the CLKCTRLn.FSWIDTH field.
PAGE 638
SAM D21 Family I2S - Inter-IC Sound Controller • 29.6.8 EXTEND for extension to the word size DMA, Interrupts and Events Table 29-4. Module Request for I2S Condition DMA request DMA request is cleared Interrupt request Receive Ready YES When data is read YES Transmit Ready (Buffer empty) YES When data is written YES Receive Overrun YES Transmit Underrun YES Event input/ output 29.6.8.
PAGE 639
SAM D21 Family I2S - Inter-IC Sound Controller individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the I2S is reset.
PAGE 640
SAM D21 Family I2S - Inter-IC Sound Controller 29.6.11 Loop-Back Mode For debugging purposes, the I2S can be configured to loop back the Transmitter to the Receiver. Writing a '1' to the Loop-Back Test Mode bit in the Serializer m Control register (SERCTRLm.RXLOOP) configures SDm as input and the remaining SD as output. Both SD will be connected internally, so the transmitted data is also received. For instance, writing SERCTRL0.RXLOOP=1 will connect SD1 output to SD0 input, or writing SERCTRL1.
PAGE 641
SAM D21 Family I2S - Inter-IC Sound Controller Figure 29-8. Time Slot Application Block Diagram MCKn SCKn I2S FSn SDO SDI Master Clock Serial Clock EXTERNAL AUDIO CODEC for First Time Slot Frame Sync Serial Data Out Serial Data In EXTERNAL AUDIO CODEC for Second Time Slot Serial Clock First Time Slot Frame Sync Second Time Slot Dstart Dend Serial Data Out Serial Data In Figure 29-9.
PAGE 642
SAM D21 Family I2S - Inter-IC Sound Controller Figure 29-10. PDM Microphones Application Block Diagram MCKn SCKn 64 fs Serial Clock EXTERNAL PDM MICROPHONE for Left Channel 2 IS FSn SDI Serial Data In L/RSEL VDD EXTERNAL PDM MICROPHONE for Right Channel L/RSEL GND Serial Clock Serial Data In © 2018 Microchip Technology Inc.
PAGE 643
SAM D21 Family I2S - Inter-IC Sound Controller 29.8 Register Summary Offset Name Bit Pos. 0x00 CTRLA 7:0 SERENx SERENx CKENx CKENx ENABLE SWRST 0x01 ...
PAGE 644
SAM D21 Family I2S - Inter-IC Sound Controller ...........continued Offset 0x30 0x34 0x34 29.9 Name DATAm0 DATAm1 RXDATA Bit Pos. 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported.
PAGE 645
SAM D21 Family I2S - Inter-IC Sound Controller 29.9.1 Control A Name: Offset: Reset: Property: Bit 7 CTRLA 0x00 0x00 PAC Write-Protection 6 Access Reset 5 4 3 2 1 0 SERENx SERENx CKENx CKENx ENABLE SWRST R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 5,4 – SERENx Serializer x Enable [x=1..0] Writing a '0' to this bit will disable the Serializer x. Writing a '1' to this bit will enable the Serializer x. Value 0 1 Description The Serializer x is disabled. The Serializer x is enabled.
PAGE 646
SAM D21 Family I2S - Inter-IC Sound Controller 29.9.2 Clock Unit n Control Name: Offset: Reset: Property: Bit Access CLKCTRLn 0x04 + n*0x04 [n=0..
PAGE 647
SAM D21 Family I2S - Inter-IC Sound Controller Bits 23:19 – MCKDIV[4:0] Master Clock Division Factor The Master Clock n is divided by (MCKDIV + 1) to obtain the Serial Clock n. Bit 18 – MCKEN Master Clock Enable Value 0 1 Description The Master Clock n division and output is disabled. The Master Clock n division and output is enabled. Bit 16 – MCKSEL Master Clock Select This field selects the source of the Master Clock n.
PAGE 648
SAM D21 Family I2S - Inter-IC Sound Controller In Burst mode, a single Data transfer starts at each Frame Sync pulse; these pulses are 1-bit wide and occur only when a Data transfer is requested. Note that the compact stereo modes (16C and 8C) are not supported in the Burst mode.
PAGE 649
SAM D21 Family I2S - Inter-IC Sound Controller 29.9.3 Interrupt Enable Clear Name: Offset: Reset: Property: Bit 15 INTENCLR 0x0C 0x0000 PAC Write-Protection 14 Access Reset Bit 7 6 Access Reset 13 12 9 8 TXURx TXURx 11 TXRDYx TXRDYx R/W R/W R/W R/W 0 0 0 0 3 10 5 4 1 0 RXORx RXORx 2 RXRDYx RXRDYx R/W R/W R/W R/W 0 0 0 0 Bits 13,12 – TXURx Transmit Underrun x Interrupt Enable [x=1..0] Writing a '0' to this bit has no effect.
PAGE 650
SAM D21 Family I2S - Inter-IC Sound Controller Writing a '1' to this bit will clear the Receive Ready x Interrupt Enable bit, which disables the Receive Ready x interrupt. Value 0 1 Description The Receive Ready x interrupt is disabled. The Receive Ready x interrupt is enabled. © 2018 Microchip Technology Inc.
PAGE 651
SAM D21 Family I2S - Inter-IC Sound Controller 29.9.4 Interrupt Enable Set Name: Offset: Reset: Property: Bit 15 INTENSET 0x10 0x0000 PAC Write-Protection 14 Access Reset Bit 7 6 Access Reset 13 12 9 8 TXURx TXURx 11 TXRDYx TXRDYx R/W R/W R/W R/W 0 0 0 0 3 10 5 4 1 0 RXORx RXORx 2 RXRDYx RXRDYx R/W R/W R/W R/W 0 0 0 0 Bits 13,12 – TXURx Transmit Underrun x Interrupt Enable [x=1..0] Writing a '0' to this bit has no effect.
PAGE 652
SAM D21 Family I2S - Inter-IC Sound Controller Writing a '1' to this bit will set the Receive Ready Interrupt Enable bit, which enables the Receive Ready interrupt. Value 0 1 Description The Receive Ready interrupt is disabled. The Receive Ready interrupt is enabled. © 2018 Microchip Technology Inc.
PAGE 653
SAM D21 Family I2S - Inter-IC Sound Controller 29.9.5 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 15 INTFLAG 0x14 0x0000 - 14 Access Reset Bit 7 6 Access Reset 13 12 9 8 TXURx TXURx 11 TXRDYx TXRDYx R/W R/W R/W R/W 0 0 0 0 3 10 5 4 1 0 RXORx RXORx 2 RXRDYx RXRDYx R/W R/W R/W R/W 0 0 0 0 Bits 13,12 – TXURx Transmit Underrun x [x=1..0] This flag is cleared by writing a '1' to it.
PAGE 654
SAM D21 Family I2S - Inter-IC Sound Controller Writing a '1' to this bit will clear the Receive Ready x interrupt flag. © 2018 Microchip Technology Inc.
PAGE 655
SAM D21 Family I2S - Inter-IC Sound Controller 29.9.6 Synchronization Busy Name: Offset: Reset: Property: Bit 9 8 DATAx DATAx Access R R Reset 0 0 Bit 15 SYNCBUSY 0x18 0x0000 - 7 14 6 13 12 11 10 5 4 3 2 1 0 SERENx SERENx CKENx CKENx ENABLE SWRST Access R R R R R R Reset 0 0 0 0 0 0 Bits 8,9 – DATAx Data x Synchronization Status [x=1..0] Bit DATAx is cleared when the synchronization of DATA Holding register (DATAx) between the clock domains is complete.
PAGE 656
SAM D21 Family I2S - Inter-IC Sound Controller 29.9.7 Serializer n Control Name: Offset: Reset: Property: Bit 31 SERCTRLn 0x20 + n*0x04 [n=0..
PAGE 657
SAM D21 Family I2S - Inter-IC Sound Controller ...........continued MONO Name Description 0x1 MONO Left channel data is duplicated to right channel Bits 23,22,21,20,18,19,18,17,16 – SLOTDISx Slot x Disabled for this Serializer [x=7..0] This field allows disabling some slots in each transmit frame: Value 0 1 Description Slot x is used for data transfer. Slot x is not used for data transfer and will be output as specified in the TXDEFAULT field.
PAGE 658
SAM D21 Family I2S - Inter-IC Sound Controller ...........continued DATASIZE[2:0] Name Description 0x3 18 18 bits 0x4 16 16 bits 0x5 16C 16 bits compact stereo 0x6 8 8 bits 0x7 8C 8 bits compact stereo Bit 7 – SLOTADJ Data Slot Formatting Adjust This field defines left or right adjustment of data samples in the slot. SLOTADJ Name Description 0x0 RIGHT Data is right adjusted in slot 0x1 LEFT Data is left adjusted in slot Bit 5 – CLKSEL Clock Unit Selection.
PAGE 659
SAM D21 Family I2S - Inter-IC Sound Controller ...........continued SERMODE[1:0] Name Description 0x2 PDM2 Receive one PDM data on each serial clock edge 0x3 © 2018 Microchip Technology Inc.
PAGE 660
SAM D21 Family I2S - Inter-IC Sound Controller 29.9.8 Data Holding m Name: Offset: Reset: Property: Bit 31 DATAm 0x30 + m*0x04 [m=0..
PAGE 661
SAM D21 Family I2S - Inter-IC Sound Controller 29.9.
PAGE 662
SAM D21 Family TC – Timer/Counter 30. TC – Timer/Counter 30.1 Overview The TC consists of a counter, a prescaler, compare/capture channels and control logic. The counter can be set to count events, or it can be configured to count clock pulses. The counter, together with the compare/capture channels, can be configured to timestamp input events, allowing capture of frequency and pulse width. It can also perform waveform generation, such as frequency generation and pulse-width modulation (PWM). 30.
PAGE 663
SAM D21 Family TC – Timer/Counter 30.3 Block Diagram Figure 30-1. Timer/Counter Block Diagram BASE COUNTER PER PRESCALER count COUNTER OVF/UNF (INT Req.) clear load CONTROL LOGIC direction ERR (INT Req.) Top = event Zero =0 Update COUNT Compare / Capture CONTROL LOGIC WAVEFORM GENERATION CC0 match MCx (INT Req.) = 30.
PAGE 664
SAM D21 Family TC – Timer/Counter Related Links 7. I/O Multiplexing and Considerations 30.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 30.5.1 I/O Lines In order to use the I/O lines of this peripheral, the I/O pins must be configured using the I/O Pin Controller (PORT). Related Links 23. PORT - I/O Pin Controller 30.5.
PAGE 665
SAM D21 Family TC – Timer/Counter 11.2 Nested Vector Interrupt Controller 30.5.6 Events The events of this peripheral are connected to the Event System. Related Links 24. EVSYS – Event System 30.5.7 Debug Operation When the CPU is halted in debug mode, this peripheral will halt normal operation. This peripheral can be forced to continue operation during debugging - refer to the Debug Control (DBGCTRL) register for details. 30.5.
PAGE 666
SAM D21 Family TC – Timer/Counter ...........continued Name Description Timer The timer/counter clock control is handled by an internal source Counter The clock control is handled externally (e.g. counting external events) CC For compare operations, the CC are referred to as “compare channels” For capture operations, the CC are referred to as “capture channels.
PAGE 667
SAM D21 Family TC – Timer/Counter 3. 4. 5. 6. 7. 8. Select one wave generation operation in the Waveform Generation Operation bit group in the Control A register (CTRLA.WAVEGEN). If desired, the GCLK_TCx clock can be prescaled via the Prescaler bit group in the Control A register (CTRLA.PRESCALER). – If the prescaler is used, select a prescaler synchronization operation via the Prescaler and Counter Synchronization bit group in the Control A register (CTRLA.PRESYNC).
PAGE 668
SAM D21 Family TC – Timer/Counter • • • COUNT8: The 8-bit TC has its own Period register (PER). This register is used to store the period value that can be used as the top value for waveform generation. COUNT16: 16-bit is the default counter mode. There is no dedicated period register in this mode. COUNT32: This mode is achieved by pairing two 16-bit TC peripherals. TC3 is paired with TC4, and TC5 is paired with TC6. TC7 does not support 32-bit resolution.
PAGE 669
SAM D21 Family TC – Timer/Counter retain its current value. All waveforms are cleared and the Stop bit in the Status register is set (STATUS.STOP). 30.6.2.5.2 Re-Trigger Command and Event Action A re-trigger command can be issued from software by writing the Command bits in the Control B Set register (CTRLBSET.CMD = 0x1, RETRIGGER), or from event when a re-trigger event action is configured in the Event Control register (EVCTRL.EVACT = 0x1, RETRIGGER).
PAGE 670
SAM D21 Family TC – Timer/Counter • • • Match frequency (MFRQ) Normal pulse-width modulation (NPWM) Match pulse-width modulation (MPWM) When using NPWM or NFRQ configuration, the TOP will be determined by the counter resolution. In 8-bit counter mode, the Period register (PER) is used as TOP, and the TOP can be changed by writing to the PER register. In 16- and 32-bit counter mode, TOP is fixed to the maximum (MAX) value of the counter. Related Links 23. PORT - I/O Pin Controller 30.6.2.6.
PAGE 671
SAM D21 Family TC – Timer/Counter For single-slope PWM generation, the period time (T) is controlled by the TOP value, and CCx controls the duty cycle of the generated waveform output. When up-counting, the WO[x] is set at start or compare match between the COUNT and TOP values, and cleared on compare match between COUNT and CCx register values.
PAGE 672
SAM D21 Family TC – Timer/Counter COUNT and TOP are continuously compared, so when a new TOP value that is lower than current COUNT is written to TOP, COUNT will wrap before a compare match. A counter wraparound can occur in any operation mode when up-counting without buffering, see the figure below. Figure 30-7.
PAGE 673
SAM D21 Family TC – Timer/Counter Figure 30-9. Input Capture Timing events TOP COUNT ZERO Capture 0 Capture 1 Capture 2 Capture 3 The TC can detect capture overflow of the input capture channels: When a new capture event is detected while the Capture Interrupt flag (INTFLAG.MCx) is still set, the new timestamp will not be stored and INTFLAG.ERR will be set. 30.6.2.7.2 Period and Pulse-Width (PPW) Capture Action The TC can perform two input captures and restart the counter on one of the edges.
PAGE 674
SAM D21 Family TC – Timer/Counter Figure 30-10. PWP Capture Period (T) Pulsewitdh (tp) external signal events MAX "capture" COUNT ZERO CC0 30.6.3 CC1 CC0 CC1 Additional Features 30.6.3.1 One-Shot Operation When one-shot is enabled, the counter automatically stops on the next counter overflow or underflow condition. When the counter is stopped, the Stop bit in the Status register (STATUS.STOP) is automatically set and the waveform outputs are set to zero.
PAGE 675
SAM D21 Family TC – Timer/Counter ...........continued Condition Interrupt request Capture Overflow Error YES Synchronizatio n Ready YES Event output Event input Start Counter YES Retrigger Counter YES Increment / Decrement counter YES Simple Capture YES Period Capture YES Pulse Width Capture YES DMA request DMA request is cleared Note: 1. Two DMA requests lines are available, one for each compare/capture channel. 30.6.4.
PAGE 676
SAM D21 Family TC – Timer/Counter Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the TC is reset.
PAGE 677
SAM D21 Family TC – Timer/Counter • Enable bit in the Control A register (CTRLA.ENABLE) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
PAGE 678
SAM D21 Family TC – Timer/Counter ...........continued Offset Name Bit Pos. 0x0E INTFLAG 7:0 0x0F STATUS 7:0 0x10 COUNT 7:0 COUNT[7:0] 0x11 Reserved 0x12 Reserved 0x13 Reserved 0x14 PER 7:0 PER[7:0] 0x15 Reserved 0x16 Reserved 0x17 Reserved MC1 SYNCBUSY MC0 SYNCRDY SLAVE STOP 0x18 CC0 7:0 CC[7:0] 0x19 CC1 7:0 CC[7:0] 0x1A Reserved 0x1B Reserved 0x1C Reserved 0x1D Reserved 0x1E Reserved 0x1F Reserved ERR OVF ENABLE SWRST Table 30-5.
PAGE 679
SAM D21 Family TC – Timer/Counter ...........continued Offset 0x18 0x19 0x1A 0x1B Name CC0 CC1 0x1C Reserved 0x1D Reserved 0x1E Reserved 0x1F Reserved Bit Pos. 7:0 CC[7:0] 15:8 CC[15:8] 7:0 CC[7:0] 15:8 CC[15:8] Table 30-6. Register Summary – 32-bit Mode Offset 0x00 0x01 0x02 0x03 Name CTRLA READREQ Bit Pos.
PAGE 680
SAM D21 Family TC – Timer/Counter 30.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-protection is denoted by the "PAC Write-Protection" property in each individual register description.
PAGE 681
SAM D21 Family TC – Timer/Counter 30.8.
PAGE 682
SAM D21 Family TC – Timer/Counter Value 0x7 Name DIV1024 Description Prescaler: GCLK_TC/1024 Bits 6:5 – WAVEGEN[1:0] Waveform Generation Operation These bits select the waveform generation operation. They affect the top value, as shown in “Waveform Output Operations”. It also controls whether frequency or PWM waveform generation should be used. How these modes differ can also be seen from “Waveform Output Operations”. These bits are not synchronized. Table 30-7.
PAGE 683
SAM D21 Family TC – Timer/Counter Value 0 1 Description The peripheral is disabled. The peripheral is enabled. Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the TC, except DBGCTRL, to their initial state, and the TC will be disabled. Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.
PAGE 684
SAM D21 Family TC – Timer/Counter 30.8.2 Read Request Name: Offset: Reset: Bit READREQ 0x02 0x0000 15 14 RREQ RCONT Access W R/W Reset 0 0 Bit 7 6 13 12 11 5 4 3 10 9 8 2 1 0 ADDR[4:0] Access Reset R/W R/W R/W R/W R/W 0 0 0 0 0 Bit 15 – RREQ Read Request Writing a zero to this bit has no effect. This bit will always read as zero. Writing a one to this bit requests synchronization of the register pointed to by the Address bit group (READREQ.
PAGE 685
SAM D21 Family TC – Timer/Counter 30.8.3 Control B Clear Name: Offset: Reset: Property: CTRLBCLR 0x04 0x00 PAC Write-Protection, Read-Synchronized, Write-Synchronized This register allows the user to clear bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set register (CTRLBSET).
PAGE 686
SAM D21 Family TC – Timer/Counter Value 1 Description The timer/counter is counting down (decrementing). © 2018 Microchip Technology Inc.
PAGE 687
SAM D21 Family TC – Timer/Counter 30.8.4 Control B Set Name: Offset: Reset: Property: CTRLBSET 0x05 0x00 PAC Write-Protection, Read-synchronized, Write-Synchronized This register allows the user to set bits in the CTRLB register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Clear register (CTRLBCLR).
PAGE 688
SAM D21 Family TC – Timer/Counter Value 1 Description The timer/counter is counting down (decrementing). © 2018 Microchip Technology Inc.
PAGE 689
SAM D21 Family TC – Timer/Counter 30.8.5 Control C Name: Offset: Reset: Property: Bit 7 CTRLC 0x06 0x00 PAC Write-Protection, Read-synchronized, Write-Synchronized 6 Access Reset 5 4 1 0 CPTENx CPTENx 3 2 INVENx INVENx R/W R/W R/W R/W 0 0 0 0 Bits 5,4 – CPTENx Capture Channel x Enable These bits are used to select the capture or compare operation on channel x. Writing a '1' to CPTENx enables capture on channel x. Writing a '0' to CPTENx disables capture on channel x.
PAGE 690
SAM D21 Family TC – Timer/Counter 30.8.6 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x08 0x00 PAC Write-Protection 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run Mode This bit is not affected by a software reset, and should not be changed by software while the TC is enabled. Value 0 1 Description The TC is halted when the device is halted in debug mode. The TC continues normal operation when the device is halted in debug mode.
PAGE 691
SAM D21 Family TC – Timer/Counter 30.8.7 Event Control Name: Offset: Reset: Property: Bit 15 EVCTRL 0x0A 0x0000 PAC Write-Protection, Enable-Protected 14 Access Reset Bit 7 6 Access Reset 13 12 MCEOx MCEOx 11 OVFEO R/W R/W R/W 0 0 0 3 10 2 9 8 5 4 TCEI TCINV 1 0 R/W R/W R/W R/W R/W 0 0 0 0 0 EVACT[2:0] Bits 13,12 – MCEOx Match or Capture Channel x Event Output Enable [x = 1..0] These bits enable the generation of an event for every match or capture on channel x.
PAGE 692
SAM D21 Family TC – Timer/Counter Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Name OFF RETRIGGER COUNT START PPW PWP - © 2018 Microchip Technology Inc.
PAGE 693
SAM D21 Family TC – Timer/Counter 30.8.8 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x0C 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 Access Reset 5 4 3 MCx MCx R/W R/W 0 0 2 1 0 SYNCRDY ERR OVF R/W R/W R/W 0 0 0 Bits 5,4 – MCx Match or Capture Channel x Interrupt Enable [x = 1.
PAGE 694
SAM D21 Family TC – Timer/Counter 30.8.9 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x0D 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 7 6 Access Reset 5 4 3 MCx MCx R/W R/W 0 0 2 1 0 SYNCRDY ERR OVF R/W R/W R/W 0 0 0 Bits 5,4 – MCx Match or Capture Channel x Interrupt Enable [x = 1..
PAGE 695
SAM D21 Family TC – Timer/Counter 30.8.10 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 INTFLAG 0x0E 0x00 - 6 Access Reset 5 4 3 1 0 MCx MCx SYNCRDY 2 ERR OVF R/W R/W R/W R/W R/W 0 0 0 0 0 Bits 5,4 – MCx Match or Capture Channel x [x = 1..0] This flag is set on a comparison match, or when the corresponding CCx register contains a valid capture value.
PAGE 696
SAM D21 Family TC – Timer/Counter 30.8.11 Status Name: Offset: Reset: Property: Bit STATUS 0x0F 0x08 - 4 3 SYNCBUSY 7 6 5 SLAVE STOP Access R R R Reset 0 0 1 2 1 0 Bit 7 – SYNCBUSY Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. Bit 4 – SLAVE Slave Status Flag This bit is only available in 32-bit mode on the slave TC (i.e.
PAGE 697
SAM D21 Family TC – Timer/Counter 30.8.12.1 Counter Value, 8-bit Mode Name: Offset: Reset: Property: Bit COUNT 0x10 0x00 PAC Write-Protection, Write-Synchronized, Read-Synchronized 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 R/W R/W R/W R/W 0 0 0 0 0 COUNT[7:0] Access Reset Bits 7:0 – COUNT[7:0] Counter Value These bits contain the current counter value. © 2018 Microchip Technology Inc.
PAGE 698
SAM D21 Family TC – Timer/Counter 30.8.12.2 Counter Value, 16-bit Mode Name: Offset: Reset: Property: Bit COUNT 0x10 0x00 PAC Write-Protection, Write-Synchronized, Read-Synchronized 15 14 13 12 11 10 9 8 R/W R/W R/W R/W Reset 0 0 R/W R/W R/W R/W 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[15:8] Access COUNT[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 – COUNT[15:0] Counter Value These bits contain the current counter value.
PAGE 699
SAM D21 Family TC – Timer/Counter 30.8.12.
PAGE 700
SAM D21 Family TC – Timer/Counter 30.8.13.1 Period Value, 8-bit Mode Name: Offset: Reset: Property: Bit PER 0x14 0xFF Write-Synchronized 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 R/W R/W R/W R/W 0 0 0 0 1 PER[7:0] Access Reset Bits 7:0 – PER[7:0] Period Value These bits hold the value of the Period Buffer register PERBUF. The value is copied to PER register on UPDATE condition. 30.8.14 Compare/Capture © 2018 Microchip Technology Inc.
PAGE 701
SAM D21 Family TC – Timer/Counter 30.8.14.1 Channel x Compare/Capture Value, 8-bit Mode Name: Offset: Reset: Property: Bit CCx 0x18+i*0x1 [i=0..1] 0x00 Write-Synchronized 7 6 5 4 3 2 1 0 R/W R/W R/W R/W 0 0 0 R/W R/W R/W R/W 0 0 0 0 0 CC[7:0] Access Reset Bits 7:0 – CC[7:0] Channel x Compare/Capture Value These bits contain the compare/capture value in 8-bit TC mode. In Match frequency (MFRQ) or Match PWM (MPWM) waveform operation (CTRLA.
PAGE 702
SAM D21 Family TC – Timer/Counter 30.8.14.2 Channel x Compare/Capture Value, 16-bit Mode Name: Offset: Reset: Property: Bit CCx 0x18+i*0x2 [i=0..
PAGE 703
SAM D21 Family TC – Timer/Counter 30.8.14.3 Channel x Compare/Capture Value, 32-bit Mode Name: Offset: Reset: Property: Bit CCx 0x18+i*0x4 [i=0..
PAGE 704
SAM D21 Family TCC – Timer/Counter for Control Applications 31. TCC – Timer/Counter for Control Applications 31.1 Overview The device provides three instances of the Timer/Counter for Control applications (TCC) peripheral, TCC[2:0]. Each TCC instance consists of a counter, a prescaler, compare/capture channels and control logic. The counter can be set to count events or clock pulses.
PAGE 705
SAM D21 Family TCC – Timer/Counter for Control Applications • • • • Block Diagram Figure 31-1. Timer/Counter for Control Applications - Block Diagram Base Counter BV PERB PER Prescaler "count" "clear" "load" "direction" Counter COUNT = OVF (INT/Event/DMA Req.) ERR (INT Req.) Control Logic TOP BOTTOM =0 "TCCx_EV0" (TCE0) "TCCx_EV1" (TCE1) "event" UPDATE "TCCx_MCx" Event System WO[7] CCx = Waveform Generation "match" © 2018 Microchip Technology Inc.
PAGE 706
SAM D21 Family TCC – Timer/Counter for Control Applications 31.4 Signal Description Pin Name Type Description TCCx/WO[0] Digital output Compare channel 0 waveform output TCCx/WO[1] Digital output Compare channel 1 waveform output … ... ... TCCx/WO[WO_NUM-1] Digital output Compare channel n waveform output Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be mapped on several pins. Related Links 7.
PAGE 707
SAM D21 Family TCC – Timer/Counter for Control Applications 31.5.4 DMA The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with this peripheral the DMAC must be configured first. Refer to DMAC – Direct Memory Access Controller for details. Related Links 20. DMAC – Direct Memory Access Controller 31.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller.
PAGE 708
SAM D21 Family TCC – Timer/Counter for Control Applications 31.6 Functional Description 31.6.1 Principle of Operation The following definitions are used throughout the documentation: Table 31-1. Timer/Counter for Control Applications - Definitions Name Description TOP The counter reaches TOP when it becomes equal to the highest value in the count sequence. The TOP value can be the same as Period (PER) or the Compare Channel 0 (CC0) register value depending on the waveform generator mode in 31.6.2.5.
PAGE 709
SAM D21 Family TCC – Timer/Counter for Control Applications Recoverable fault sources can be filtered and/or windowed to avoid false triggering, for example from I/O pin glitches, by using digital filtering, input blanking, and qualification options. See also 31.6.3.5 Recoverable Faults.
PAGE 710
SAM D21 Family TCC – Timer/Counter for Control Applications Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but not at the same time as CTRLA.ENABLE is written to '0'. Enable-protection is denoted by the “Enable-Protected” property in the register description. Before the TCC is enabled, it must be configured as outlined by the following steps: 1. Enable the TCC bus clock (CLK_TCCx_APB). 2.
PAGE 711
SAM D21 Family TCC – Timer/Counter for Control Applications 31.6.2.4 Counter Operation Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at each TCC clock input (CLK_TCC_COUNT). A counter clear or reload mark the end of current counter cycle and the start of a new one. The counting direction is set by the Direction bit in the Control B register (CTRLB.DIR). If the bit is zero, it's counting up and one if counting down.
PAGE 712
SAM D21 Family TCC – Timer/Counter for Control Applications When a pause is detected, the counter can stop immediatly maintaining its current value and all waveforms keep their current state, as long as a start event action is detected: Input Event Action 0 bits in Event Control register (EVCTRL.EVACT0=0x3, START). Re-Trigger Command and Event Action A re-trigger command can be issued from software by using TCC Command bits in Control B Set register (CTRLBSET.
PAGE 713
SAM D21 Family TCC – Timer/Counter for Control Applications The decrement event action can be selected in the Event Control register (EVCTRL.EVACT1=0x4, DEC) and can change the counter state when an event is received. When the TCE1 (TCCx_EV1) event is received, the counter decrements, whatever the direction setting (CTRLBSET.DIR or CTRLBCLR.DIR) is. Non-recoverable Fault Event Action Non-recoverable fault actions can be selected in the Event Control register (EVCTRL.EVACTn=0x7, FAULT).
PAGE 714
SAM D21 Family TCC – Timer/Counter for Control Applications • • • • • Normal Pulse-Width Modulation (NPWM) Dual-slope, interrupt/event at TOP (DSTOP) Dual-slope, interrupt/event at ZERO (DSBOTTOM) Dual-slope, interrupt/event at Top and ZERO (DSBOTH) Dual-slope, critical interrupt/event at ZERO (DSCRITICAL) When using MFRQ configuration, the TOP value is defined by the CC0 register value. For the other waveform operations, the TOP value is defined by the Period (PER) register value.
PAGE 715
SAM D21 Family TCC – Timer/Counter for Control Applications Figure 31-4. Normal Frequency Operation Period (T) Direction Change COUNT Written MAX COUNT "reload" update "clear" update "match" TOP CCx ZERO WO[x] 31.6.2.5.3 Match Frequency (MFRQ) For Match Frequency generation, the period time (T) is controlled by CC0 register instead of PER. WO[0] toggles on each update condition. Figure 31-5.
PAGE 716
SAM D21 Family TCC – Timer/Counter for Control Applications The following equation calculates the exact resolution for a single-slope PWM (RPWM_SS) waveform: �PWM_SS = log(TOP+1) log(2) �PWM_SS = �GCLK_TCC N(TOP+1) The PWM frequency depends on the Period register value (PER) and the peripheral clock frequency (fGCLK_TCC), and can be calculated by the following equation: Where N represents the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024). 31.6.2.5.
PAGE 717
SAM D21 Family TCC – Timer/Counter for Control Applications N represents the prescaler divider used. Note: In DSTOP, DSBOTTOM and DSBOTH operation, when TOP is lower than MAX/2, the CCx MSB bit defines the ramp on which the CCx Match interrupt or event is generated. (Rising if CCx[MSB] = 0, falling if CCx[MSB] = 1.) Related Links 31.6.3.2 Circular Buffer 31.6.2.5.7 Dual-Slope Critical PWM Generation Critical mode generation allows generation of non-aligned centered pulses.
PAGE 718
SAM D21 Family TCC – Timer/Counter for Control Applications In Normal and Match Frequency, the WAVE.POLx value represents the initial state of the waveform output. 31.6.2.6 Double Buffering The Pattern (PATT), Waveform (WAVE), Period (PER) and Compare Channels (CCx) registers are all double buffered.
PAGE 719
SAM D21 Family TCC – Timer/Counter for Control Applications Figure 31-10. Unbuffered Single-Slope Up-Counting Operation Counter Wraparound MAX "clear" update "write" COUNT ZERO New value written to PER that is higher than current COUNT New value written to PER that is lower than current COUNT Figure 31-11.
PAGE 720
SAM D21 Family TCC – Timer/Counter for Control Applications Figure 31-13. Changing the Period Using Buffering MAX "reload" update "write" COUNT ZERO New value written to PERB that is higher than current COUNT New value written to PERB that is lower than current COUNT PER is updated with PERB value. 31.6.2.7 Capture Operations To enable and use capture operations, the Match or Capture Channel x Event Input Enable bit in the Event Control register (EVCTRL.MCEIx) must be written to '1'.
PAGE 721
SAM D21 Family TCC – Timer/Counter for Control Applications Figure 31-15. Capture Double Buffering "capture" COUNT BV EN CCBx IF EN CCx "INT/DMA request" data read The TCC can detect capture overflow of the input capture channels: When a new capture event is detected while the Capture Buffer Valid flag (STATUS.CCBV) is still set, the new timestamp will not be stored and INTFLAG.ERR will be set.
PAGE 722
SAM D21 Family TCC – Timer/Counter for Control Applications The corresponding capture is done only if the channel is enabled in capture mode (CTRLA.CPTENx=1). If not, the capture action will be ignored and the channel will be enabled in compare mode of operation. When only one of these channel is required, the other channel can be used for other purposes. The TCC can detect capture overflow of the input capture channels: When a new capture event is detected while the INTFLAG.
PAGE 723
SAM D21 Family TCC – Timer/Counter for Control Applications Dithering consists in adding some extra clocks cycles in a frame of several PWM cycles, and can improve the accuracy of the average output pulse width and period. The extra clock cycles are added on some of the compare match signals, one at a time, through a "blue noise" process that minimizes the flickering on the resulting dither patterns.
PAGE 724
SAM D21 Family TCC – Timer/Counter for Control Applications DITH5 mode: ��ℎ = DITHERCY 1 + CCx 32 �GCLK_TCC ��ℎ = DITHERCY 1 + CCx 64 �GCLK_TCC DITH6 mode: Note: The PWM period will remain static in this case. 31.6.3.4 Ramp Operations Three ramp operation modes are supported. All of them require the timer/counter running in single-slope PWM generation. The ramp mode is selected by writing to the Ramp Mode bits in the Waveform Control register (WAVE.RAMP).
PAGE 725
SAM D21 Family TCC – Timer/Counter for Control Applications Alternate RAMP2 (RAMP2A) Operation Alternate RAMP2 operation is similar to RAMP2, but CC0 controls both WO[0] and WO[1] waveforms when the corresponding circular buffer option is enabled (CIPEREN=1). The waveform polarity is the same on both outputs. Channel 1 can be used in capture mode. Figure 31-19.
PAGE 726
SAM D21 Family TCC – Timer/Counter for Control Applications Figure 31-21. RAMP2 Critical Operation With 2 Channels Ramp A B A TOP CC0 B Retrigger on FaultA CC1 COUNT "clear" update "match" TOP CC1 ZERO WO[0] POL0 = 0 WO[1] Keep on FaultB POL1 = 1 FaultA input FaultB input 31.6.3.5 Recoverable Faults Recoverable faults can restart or halt the timer/counter. Two faults, called Fault A and Fault B, can trigger recoverable fault actions on the compare channels CC0 and CC1 of the TCC.
PAGE 727
SAM D21 Family TCC – Timer/Counter for Control Applications 1 + BLANKVAL �GCLK_TCCx_PRESC Here, fGCLK_TCCx_PRESC is the frequency of the prescaled peripheral clock frequency fGCLK_TCCx. �� = The maximum blanking time (FCTRLn.BLANKVAL= 255) at fGCLK_TCCx=96MHz is 2.67µs (no prescaler) or 170µs (prescaling). For fGCLK_TCCx=1MHz, the maximum blanking time is either 170µs (no prescaling) or 10.9ms (prescaling enabled). Figure 31-22.
PAGE 728
SAM D21 Family TCC – Timer/Counter for Control Applications Figure 31-24.
PAGE 729
SAM D21 Family TCC – Timer/Counter for Control Applications Figure 31-26. Waveform Generation in RAMP1 mode with Restart Action MAX "clear" update "match" TOP CC0 COUNT CC1 ZERO Restart Restart Fault Input A WO[0] WO[1] Figure 31-27.
PAGE 730
SAM D21 Family TCC – Timer/Counter for Control Applications CCx Content: In CAPTMIN and CAPTMAX operations, CCx keeps the respective extremum captured values, see Figure 31-28. In LOCMIN, LOCMAX or DERIV0 operation, CCx follows the counter value at fault time, see Figure 31-29. Before enabling CAPTMIN or CAPTMAX mode of capture, the user must initialize the corresponding CCx register value to a value different from zero (for CAPTMIN) top (for CAPTMAX).
PAGE 731
SAM D21 Family TCC – Timer/Counter for Control Applications Figure 31-29. Capture Action “DERIV0” TOP COUNT "update" "match" CC0 ZERO WO[0] FaultA Input CC0 Event/ Interrupt Hardware This is configured by writing 0x1 to the Fault n Halt mode bits in the Recoverable Fault n Halt Action Configuration register (FCTRLn.HALT). When enabled, the timer/counter is halted and the cycle is extended as long as the corresponding fault is present.
PAGE 732
SAM D21 Family TCC – Timer/Counter for Control Applications Figure 31-31. Waveform Generation with Fault Qualification, Halt, and Restart Actions MAX "update" "match" TOP CC0 COUNT HALT ZERO Resume Fault A Input Qual -  - -  -  x  x - x Fault Input A KEEP WO[0] Software Halt Action This is configured by writing 0x2 to the Fault n Halt mode bits in the Recoverable Fault n configuration register (FCTRLn.HALT).
PAGE 733
SAM D21 Family TCC – Timer/Counter for Control Applications (DRVCTRL.FILTERVALn). Therefore, the event detection is synchronous, and event action is delayed by the selected digital filter value clock cycles. When the Fault Detection on Debug Break Detection bit in Debug Control register (DGBCTRL.FDDBD) is written to '1', a non-recoverable Debug Faults State and an interrupt (DFS) is generated when the system goes in debug operation.
PAGE 734
SAM D21 Family TCC – Timer/Counter for Control Applications 0 is duplicated to the Output matrix output OTMX[CC_NUM], channel 1 to OTMX[CC_NUM+1] and so on. • Configuration 0x1 distributes the channels on output modulo half the number of channels. This assigns twice the number of output locations to the lower channels than the default configuration. This can be used, for example, to control the four transistors of a full bridge using only two compare channels.
PAGE 735
SAM D21 Family TCC – Timer/Counter for Control Applications As shown in Figure 31-35, the 8-bit dead-time counter is decremented by one for each peripheral clock cycle until it reaches zero. A non-zero counter value will force both the low side and high side outputs into their OFF state. When the output matrix (OTMX) output changes, the dead-time counter is reloaded according to the edge of the input.
PAGE 736
SAM D21 Family TCC – Timer/Counter for Control Applications 31.6.4 DMA, Interrupts, and Events Table 31-6.
PAGE 737
SAM D21 Family TCC – Timer/Counter for Control Applications Counter overflow (OVF) If the Ones-shot Trigger mode in the control A register (CTRLA.DMAOS) is written to '0', the TCC generates a DMA request on each cycle when an update condition (overflow, underflow or re-trigger) is detected. When an update condition (overflow, underflow or re-trigger) is detected while CTRLA.DMAOS=1, the TCC generates a DMA trigger on the cycle following the DMA One-Shot Command written to the Control B register (CTRLBSET.
PAGE 738
SAM D21 Family TCC – Timer/Counter for Control Applications Figure 31-37. DMA Triggers in RAMP and RAMP2 Operation Mode and Circular Buffer Enabled Ramp A Cycle B A B A B N-1 N-2 N "update" COUNT ZERO STATUS.IDX DMA_CCx_req DMA Channel i Update ramp A DMA_OVF_req DMA Channel j Update ramp B DMA Operation with Circular Buffer in DSBOTH Mode When a CC channel is selected as a circular buffer, the related DMA request is not set on a compare match detection, but on start of down-counting phase.
PAGE 739
SAM D21 Family TCC – Timer/Counter for Control Applications • • • • • • • Count (CNT) - refer also to description of EVCTRL.CNTSEL. Capture Overflow Error (ERR) Non-Recoverable Update Fault (UFS) Debug Fault State (DFS) Recoverable Faults (FAULTn) Non-recoverable Faults (FAULTx) Compare Match or Capture Channels (MCx) These interrupts are asynchronous wake-up sources. See Sleep Mode Entry and Exit Table in PM/Sleep Mode Controller section for details.
PAGE 740
SAM D21 Family TCC – Timer/Counter for Control Applications • Non-recoverable fault The TCC can take the following actions on counter Event 0 (TCCx EV0): • Counter re-trigger • Count on event (increment or decrement, depending on counter direction) • Counter start - start counting on the event rising edge. Further events will not restart the counter; the counter will keep on counting using prescaled GCLK_TCCx, until it reaches TOP or ZERO, depending on the direction. • Counter increment on event.
PAGE 741
SAM D21 Family TCC – Timer/Counter for Control Applications • • • • • Count Value register (COUNT): synchronization is done on demand through READSYNC command (CTRLBSET.
PAGE 742
SAM D21 Family TCC – Timer/Counter for Control Applications 31.7 Offset Register Summary Name Bit Pos. 7:0 RESOLUTION[1:0] 15:8 ALOCK ENABLE PRESCYNC[1:0] RUNSTDBY SWRST PRESCALER[2:0] 0x00 CTRLA CPTEN2 CPTEN1 CPTEN0 0x04 CTRLBCLR 7:0 CMD[2:0] IDXCMD[1:0] ONESHOT LUPD DIR 0x05 CTRLBSET 7:0 CMD[2:0] IDXCMD[1:0] ONESHOT LUPD DIR STATUS CTRLB ENABLE SWRST CC3 CC2 CC1 CC0 CCB1 CCB0 PERB WAVEB PATTB QUAL KEEP 23:16 31:24 CPTEN3 0x06 ...
PAGE 743
SAM D21 Family TCC – Timer/Counter for Control Applications ...........continued Offset Name Bit Pos.
PAGE 744
SAM D21 Family TCC – Timer/Counter for Control Applications ...........continued Offset Name Bit Pos. 0x54 ... Reserved 0x63 0x64 PATTB 7:0 PGEB0[7:0] 15:8 PGVB0[7:0] 0x66 ...
PAGE 745
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.
PAGE 746
SAM D21 Family TCC – Timer/Counter for Control Applications Value Name Description Counter Reloaded Prescaler 0x0 GCLK Reload or reset Counter on next GCLK - 0x1 PRESC Reload or reset Counter on next prescaler clock - 0x2 RESYNC Reload or reset Counter on next GCLK Reset prescaler counter 0x3 Reserved Bit 11 – RUNSTDBY Run in Standby This bit is used to keep the TCC running in standby mode. This bit is not synchronized. Value 0 1 Description The TCC is halted in standby.
PAGE 747
SAM D21 Family TCC – Timer/Counter for Control Applications ...........continued Value Name Description 0x2 DITH5 Dithering is done every 32 PWM frames. PER[4:0] and CCx[4:0] contain dithering pattern selection. 0x3 DITH6 Dithering is done every 64 PWM frames. PER[5:0] and CCx[5:0] contain dithering pattern selection. Bit 1 – ENABLE Enable Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/ disabled. The value written to CTRLA.
PAGE 748
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.2 Control B Clear Name: Offset: Reset: Property: CTRLBCLR 0x04 0x00 PAC Write-Protection, Write-Synchronized, Read-Synchronized This register allows the user to change this register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set (CTRLBSET) register.
PAGE 749
SAM D21 Family TCC – Timer/Counter for Control Applications Writing a '1' to this bit will disable the one-shot operation. Value 0 1 Description The TCC will update the counter value on overflow/underflow condition and continue operation. The TCC will stop counting on the next underflow/overflow condition. Bit 1 – LUPD Lock Update This bit controls the update operation of the TCC buffered registers. When CTRLB.
PAGE 750
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.3 Control B Set Name: Offset: Reset: Property: CTRLBSET 0x05 0x00 PAC Write-Protection, Write-Synchronized, Read-Synchronized This register allows the user to change this register without doing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set (CTRLBCLR) register.
PAGE 751
SAM D21 Family TCC – Timer/Counter for Control Applications Writing a '1' to this bit will enable the one-shot operation. Value 0 1 Description The TCC will count continuously. The TCC will stop counting on the next underflow/overflow condition. Bit 1 – LUPD Lock Update This bit controls the update operation of the TCC buffered registers. When CTRLB.LUPD is set, the hardware UPDATE registers with value from their buffered registers is disabled.
PAGE 752
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.
PAGE 753
SAM D21 Family TCC – Timer/Counter for Control Applications Bits 8, 9, 10, 11 – CC Compare/Capture Channel x Synchronization Busy This bit is cleared when the synchronization of Compare/Capture Channel x register between the clock domains is complete. This bit is set when the synchronization of Compare/Capture Channel x register between clock domains is started. CCx bit is available only for existing Compare/Capture Channels. For details on CC channels number, refer to each TCC feature list.
PAGE 754
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.5 Fault Control A and B Name: Offset: Reset: Property: Bit FCTRLA, FCTRLB 0x0C + n*0x04 [n=0..
PAGE 755
SAM D21 Family TCC – Timer/Counter for Control Applications ...........continued Value 0x2 Name Description CAPTMIN On rising edge of a valid recoverable Fault n, capture counter value on channel selected by CHSEL[1:0], if COUNT value is lower than the last stored capture value (CC). INTFLAG.FAULTn flag rises on each local minimum detection.
PAGE 756
SAM D21 Family TCC – Timer/Counter for Control Applications Value 0 1 Description Fault n restart action is disabled. Fault n restart action is enabled. Bits 6:5 – BLANK[1:0] Recoverable Fault n Blanking Operation These bits, select the blanking start point for recoverable Fault n.
PAGE 757
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.
PAGE 758
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.
PAGE 759
SAM D21 Family TCC – Timer/Counter for Control Applications Value 0 1 Description Non-recoverable fault tri-state the output. Non-recoverable faults set the output to NRVx level. © 2018 Microchip Technology Inc.
PAGE 760
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.8 Debug control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x1E 0x00 PAC Write-Protection 6 5 4 3 Access Reset 2 1 0 FDDBD DBGRUN R/W R/W 0 0 Bit 2 – FDDBD Fault Detection on Debug Break Detection This bit is not affected by software reset and should not be changed by software while the TCC is enabled. By default this bit is zero, and the on-chip debug (OCD) fault protection is disabled.
PAGE 761
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.
PAGE 762
SAM D21 Family TCC – Timer/Counter for Control Applications Value 1 Description Incoming event x is enabled. Bits 13,12 – TCINVx Timer/Counter Event x Invert Enable This bit inverts the event x input. Value 0 1 Description Input event source x is not inverted. Input event source x is inverted. Bit 10 – CNTEO Timer/Counter Event Output Enable This bit is used to enable the counter cycle event. When enabled, an event will be generated on begin or end of counter cycle depending of CNTSEL[1:0] settings.
PAGE 763
SAM D21 Family TCC – Timer/Counter for Control Applications Value 0x3 0x4 0x5 0x6 0x7 Name STOP DEC PPW PWP FAULT Description Stop TC on event Decrement TC on event Period captured into CC0 Pulse Width on CC1 Period captured into CC1 Pulse Width on CC0 Non-recoverable Fault Bits 2:0 – EVACT0[2:0] Timer/Counter Event Input 0 Action These bits define the action the TCC will perform on TCE0 event input 0.
PAGE 764
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.10 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x24 0x00000000 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
PAGE 765
SAM D21 Family TCC – Timer/Counter for Control Applications Bit 14 – FAULT0 Non-Recoverable Fault x Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables the Non-Recoverable Fault x interrupt. Value 0 1 Description The Non-Recoverable Fault x interrupt is disabled. The Non-Recoverable Fault x interrupt is enabled.
PAGE 766
SAM D21 Family TCC – Timer/Counter for Control Applications Writing a '1' to this bit will clear the Error Interrupt Disable/Enable bit, which disables the Compare interrupt. Value 0 1 Description The Error interrupt is disabled. The Error interrupt is enabled. Bit 2 – CNT Counter Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Counter Interrupt Disable/Enable bit, which disables the Counter interrupt.
PAGE 767
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.11 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x28 0x00000000 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
PAGE 768
SAM D21 Family TCC – Timer/Counter for Control Applications Bit 14 – FAULT0 Non-Recoverable Fault x Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables the Non-Recoverable Fault x interrupt. Value 0 1 Description The Non-Recoverable Fault x interrupt is disabled. The Non-Recoverable Fault x interrupt is enabled.
PAGE 769
SAM D21 Family TCC – Timer/Counter for Control Applications Writing a '1' to this bit will set the Error Interrupt Disable/Enable bit, which enables the Compare interrupt. Value 0 1 Description The Error interrupt is disabled. The Error interrupt is enabled. Bit 2 – CNT Counter Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Counter interrupt. Value 0 1 Description The Counter interrupt is disabled.
PAGE 770
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.
PAGE 771
SAM D21 Family TCC – Timer/Counter for Control Applications Value 1 Description The Non-Recoverable Fault x interrupt is enabled. Bit 13 – FAULTB Recoverable Fault B Interrupt Flag This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault B occurs. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Recoverable Fault B interrupt flag.
PAGE 772
SAM D21 Family TCC – Timer/Counter for Control Applications Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Overflow interrupt flag. © 2018 Microchip Technology Inc.
PAGE 773
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.
PAGE 774
SAM D21 Family TCC – Timer/Counter for Control Applications STATEx bit. For further details on timer/counter commands, refer to available commands description (31.8.3 CTRLBSET.CMD). Bit 13 – FAULTB Recoverable Fault B State This bit is set by hardware as soon as recoverable Fault B condition occurs. This bit can be clear by hardware when Fault B action is resumed, or by writing a '1' to this bit when the corresponding FAULTBIN bit is low. If software halt command is enabled (FAULTB.
PAGE 775
SAM D21 Family TCC – Timer/Counter for Control Applications When the bit is set, the waveforms state depend on DRVCTRL.NRE and DRVCTRL.NRV registers. Bit 1 – IDX Ramp Index In RAMP2 and RAMP2A operation, the bit is cleared during the cycle A and set during the cycle B. In RAMP1 operation, the bit always reads zero. For details on ramp operations, refer to 31.6.3.4 Ramp Operations.
PAGE 776
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.14 Counter Value Name: Offset: Reset: Property: COUNT 0x34 0x00000000 PAC Write-Protection, Write-Synchronized, Read-Synchronized Note: Prior to any read access, this register must be synchronized by user by writing the according TCC Command value to the Control B Set register (CTRLBSET.CMD=READSYNC).
PAGE 777
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.
PAGE 778
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.
PAGE 779
SAM D21 Family TCC – Timer/Counter for Control Applications Bit 7 – CIPEREN Circular Period Enable Setting this bits enable the period circular buffer option. When the bit is set, the PER register value is copied-back into the PERB register on UPDATE condition. Bits 5:4 – RAMP[1:0] Ramp Operation These bits select Ramp operation (RAMP). These bits are not synchronized. Value 0x0 0x1 0x2 0x3 0x4 Name RAMP1 RAMP2A RAMP2 RAMP2C. This bit is only available in variant L devices.
PAGE 780
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.
PAGE 781
SAM D21 Family TCC – Timer/Counter for Control Applications CTRLA.RESOLUTION Bits [n:0] 0x0 - NONE - 0x1 - DITH4 3:0 0x2 - DITH5 4:0 0x3 - DITH6 5:0 (depicted) © 2018 Microchip Technology Inc.
PAGE 782
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.18 Compare/Capture Channel x Name: Offset: Reset: Property: CC 0x44 + n*0x04 [n=0..3] 0x00000000 Write-Synchronized, Read-Synchronized The CCx register represents the 16-, 24- bit value, CCx. The register has two functions, depending of the mode of operation. For capture operation, this register represents the second buffer level and access point for the CPU and DMA.
PAGE 783
SAM D21 Family TCC – Timer/Counter for Control Applications ...........continued CTRLA.RESOLUTION Bits [23:m] 0x1 - DITH4 23:4 0x2 - DITH5 23:5 0x3 - DITH6 23:6 (depicted) Bits 5:0 – DITHER[5:0] Dithering Cycle Number These bits hold the number of extra cycles that are added on the PWM pulse width every 64 PWM frames. Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION): CTRLA.
PAGE 784
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.
PAGE 785
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.
PAGE 786
SAM D21 Family TCC – Timer/Counter for Control Applications Value 0x1 0x2 0x3 0x4 Name RAMP2A RAMP2 RAMP2C. This bit is only available in variant L devices. Refer to Configuration Summary for more information. - Description Alternative RAMP2 operation RAMP2 operation Critical RAMP2 operation Reserved Bits 2:0 – WAVEGENB[2:0] Waveform Generation Operation Buffer These register bits are the buffer bits for WAVEGEN register bits.
PAGE 787
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.
PAGE 788
SAM D21 Family TCC – Timer/Counter for Control Applications CTRLA.RESOLUTION Bits [n:0] 0x0 - NONE - 0x1 - DITH4 3:0 0x2 - DITH5 4:0 0x3 - DITH6 5:0 (depicted) © 2018 Microchip Technology Inc.
PAGE 789
SAM D21 Family TCC – Timer/Counter for Control Applications 31.8.22 Channel x Compare/Capture Buffer Value Name: Offset: Reset: Property: CCB 0x70 + n*0x04 [n=0..
PAGE 790
SAM D21 Family TCC – Timer/Counter for Control Applications Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the Control A register (CTRLA.RESOLUTION): CTRLA.RESOLUTION Bits [n:0] 0x0 - NONE - 0x1 - DITH4 3:0 0x2 - DITH5 4:0 0x3 - DITH6 5:0 (depicted) © 2018 Microchip Technology Inc.
PAGE 791
SAM D21 Family USB – Universal Serial Bus 32. USB – Universal Serial Bus 32.1 Overview The Universal Serial Bus interface (USB) module complies with the Universal Serial Bus (USB) 2.1 specification supporting both device and embedded host modes. The USB device mode supports 8 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of 16 endpoints. Each endpoint is fully configurable in any of the four transfer types: control, interrupt, bulk or isochronous.
PAGE 792
SAM D21 Family USB – Universal Serial Bus – – – – – 32.3 No pipe size limitations Supports multiplexed virtual pipe on one physical pipe to allow an unlimited USB tree Built-in DMA with multi-packet support and dual bank for all pipes Supports feedback endpoint Supports the USB 2.0 Phase-locked SOFs feature USB Block Diagram Figure 32-1.
PAGE 793
SAM D21 Family USB – Universal Serial Bus 32.5.1 I/O Lines The USB pins may be multiplexed with the I/O lines Controller. The user must first configure the I/O Controller to assign the USB pins to their peripheral functions. A 1kHz SOF clock is available on an external pin. The user must first configure the I/O Controller to assign the 1kHz SOF clock to the peripheral function. The SOF clock is available for device and host mode. 32.5.
PAGE 794
SAM D21 Family USB – Universal Serial Bus 32.5.7 Debug Operation When the CPU is halted in debug mode the USB peripheral continues normal operation. If the USB peripheral is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 32.5.
PAGE 795
SAM D21 Family USB – Universal Serial Bus Figure 32-2. General States HW RESET | CTRLA.SWRST Any state Idle CTRLA.ENABLE = 1 CTRLA.MODE =0 CTRLA.ENABLE = 0 CTRLA.ENABLE = 1 CTRLA.MODE =1 CTRLA.ENABLE = 0 Device Host After a hardware reset, the USB is in the idle state. In this state: • • • • The module is disabled. The USB Enable bit in the Control A register (CTRLA.ENABLE) is reset. The module clock is stopped in order to minimize power consumption. The USB pad is in suspend mode.
PAGE 796
SAM D21 Family USB – Universal Serial Bus Refer to 32.6.2 USB Device Operations for the basic operation of the device mode. Refer to 32.6.3 Host Operations for the basic operation of the host mode. Related Links 10.3.2 NVM Software Calibration Area Mapping 32.6.2 USB Device Operations This section gives an overview of the USB module device operation during normal transactions. For more details on general USB and USB protocol, refer to the Universal Serial Bus specification revision 2.1. 32.6.2.
PAGE 797
SAM D21 Family USB – Universal Serial Bus The application software provides the size and address of the RAM buffer to be proceeded by the USB module for a specific endpoint, and the USB module will split the buffer in the required USB data transfers without any software intervention. Figure 32-3. Multi-Packet Feature - Reduction of CPU Overhead Data Payload Without Multi-packet support Transfer Complete Interrupt & Data Processing Maximum Endpoint size With Multi-packet support 32.6.2.
PAGE 798
SAM D21 Family USB – Universal Serial Bus When the EPCFG.EPTYPE0 matches, the USB module then fetches the Data Buffer Address (ADDR) from the addressed endpoint's descriptor and waits for a DATA0 packet. If a PID error or any other PID than DATA0 is detected, the USB module returns to idle and waits for the next token packet. When the data PID matches and if the Received Setup Complete interrupt bit in the Device Endpoint Interrupt Flag register (EPINTFLAG.
PAGE 799
SAM D21 Family USB – Universal Serial Bus When an OUT token is detected, and the device address of the token packet does not match DADD.DADD, the packet is discarded and the USB module returns to idle and waits for the next token packet. If the address matches, the USB module checks if the endpoint number received is enabled in the EPCFG of the addressed endpoint. If the addressed endpoint is disabled, the packet is discarded and the USB module returns to idle and waits for the next token packet.
PAGE 800
SAM D21 Family USB – Universal Serial Bus PCKSIZE.MULTI_PACKET_SIZE. This value must be a multiple of PCKSIZE.SIZE, otherwise excess data may be written to SRAM locations used by other parts of the application. EPSTATUS.DTGLOUT management for non-isochronous packets and EPINTFLAG.BK1RDY/BK0RDY management are as for normal operation. If a maximum payload size packet is received, PCKSIZE.BYTE_COUNT will be incremented by PCKSIZE.SIZE after the transaction has completed, and EPSTATUS.
PAGE 801
SAM D21 Family USB – Universal Serial Bus If EPSTATUS.STALLRQ1 in EPSTATUS is set, and the endpoint is not isochronous, a STALL handshake is returned to the host and EPINTFLAG.STALL1 is set. If EPSTATUS.BK1RDY is cleared, the flag EPINTFLAG.TRFAIL1 is set. If the endpoint is not isochronous, a NAK handshake is returned to the host. The USB module then fetches the Data Buffer Address (ADDR) from the addressed endpoint's descriptor.
PAGE 802
SAM D21 Family USB – Universal Serial Bus Figure 32-6. Ping-Pong Overview Endpoint single bank Without Ping Pong t Endpoint dual bank Bank0 With Ping Pong Bank1 t USB data packet Available time for data processing by CPU to avoid NACK The Bank Select flag in EPSTATUS.CURBK indicates which bank data will be used in the next transaction, and is updated after each transaction. According to EPSTATUS.CURBK, EPINTFLAG.TRCPT0 or EPINTFLAG.TRFAIL0 or EPINTFLAG.TRCPT1 or EPINTFLAG.
PAGE 803
SAM D21 Family USB – Universal Serial Bus Figure 32-7. Pad Behavior Idle CTRLA.ENABLE = 0 | CTRLB.DETACH = 1 | INTFLAG.SUSPEND = 1 CTRLA.ENABLE = 1 | CTRLB.DETACH = 0 | INTFLAG.SUSPEND = 0 Active In Idle state, the pad is in Low Power Consumption mode. In Active state, the pad is active. The following figure, Pad Events, illustrates the pad events leading to a PAD state change. © 2018 Microchip Technology Inc.
PAGE 804
SAM D21 Family USB – Universal Serial Bus Figure 32-8. Pad Events Suspend detected Cleared on Wakeup Wakeup detected Active Cleared by software to acknowledge the interrupt Idle Active The Suspend Interrupt bit in the Device Interrupt Flag register (INTFLAG.SUSPEND) is set when a USB Suspend state has been detected on the USB bus. The USB pad is then automatically put in the Idle state. The detection of a non-idle state sets the Wake Up Interrupt bit (INTFLAG.WAKEUP) and wakes the USB pad.
PAGE 805
SAM D21 Family USB – Universal Serial Bus In the case where the CTRLB.UPRSM bit is set while a host initiated downstream resume is already started, the CTRLB.UPRSM is cleared and the upstream resume request is ignored. 32.6.2.15 Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Device The LPM Handshake bit in CTRLB.LPMHDSK should be configured to accept the LPM transaction.
PAGE 806
SAM D21 Family USB – Universal Serial Bus 32.6.2.16 USB Device Interrupt Figure 32-9. Device Interrupt EPINTFLAG7.STALL EPINTENSET7.STALL0/STALL1 EPINTFLAG7.TRFAIL1 EPINTENSET7.TRFAIL1 EPINTFLAG7.TRFAIL0 EPINTSMRY EPINTENSET7.TRFAIL0 ENDPOINT7 EPINTFLAG7.RXSTP EPINT7 EPINTENSET7.RXSTP EPINT6 EPINTFLAG7.TRCPT1 EPINTENSET7.TRCPT1 EPINTFLAG7.TRCPT0 EPINTENSET7.TRCPT0 USB EndPoint Interrupt EPINTFLAG0.STALL EPINTENSET0.STALL0/STALL1 EPINTFLAG0.TRFAIL1 EPINTENSET0.TRFAIL1 EPINTFLAG0.TRFAIL0 EPINTENSET0.
PAGE 807
SAM D21 Family USB – Universal Serial Bus 32.6.3 Host Operations This section gives an overview of the USB module Host operation during normal transactions. For more details on general USB and USB protocol, refer to Universal Serial Bus Specification revision 2.1. 32.6.3.1 Device Detection and Disconnection Prior to device detection the software must set the VBUS is OK bit (CTRLB.VBUSOK) register when the VBUS is available. This notifies the USB host that USB operations can be started.
PAGE 808
SAM D21 Family USB – Universal Serial Bus known values before using the pipe, so that the USB controller does not read the random values from the RAM. The Pipe Size field in the Packet Size register (PCKSIZE.SIZE) should be configured as per the size reported by the device for the endpoint associated with this pipe. The Address of Data Buffer register (ADDR) should be set to the data buffer used for pipe transfers. The Pipe Bank bit (PCFG.BK) should be set to one if dual banking is desired.
PAGE 809
SAM D21 Family USB – Universal Serial Bus suspend state by sending a Downstream Resume on the USB bus (CTRLB.RESUME set to 1). In both cases, when the downstream resume is completed, the CTRLB.SOFE bit is automatically set and the host enters again the active state. 32.6.3.8 Phase-locked SOFs To support the Synchronous Endpoints capability, the period of the emitted Start-of-Frame is maintained while the USB connection is not in the active state.
PAGE 810
SAM D21 Family USB – Universal Serial Bus The user can follow the current bank looking at Current Bank bit in PSTATUS (PSTATUS.CURBK) and by looking at Data Toggle for IN pipe bit in PSTATUS (PSTATUS.DTGLIN). When the pipe is configured as single bank (Pipe Bank bit in PCFG (PCFG.BK) is 0), only PINTFLAG.TRCPT0 and PSTATUS.BK0 are used. When the pipe is configured as dual bank (PCFG.BK is 1), both PINTFLAG.TRCPT0/1 and PSTATUS.BK0/1 are used. 32.6.3.
PAGE 811
SAM D21 Family USB – Universal Serial Bus stage if the USB detects a corrupted packet. The IN packet will remain stored in the bank and PINTFLAG.TRCPT0/1 will be set. 32.6.3.15 PERR Error This error exists for all pipes. It sets the PINTFLAG.PERR Interrupt, which triggers an interrupt if PINTFLAG.PERR is set. The user must check the PINTSMRY register to find out the pipe which can cause an interrupt.
PAGE 812
SAM D21 Family USB – Universal Serial Bus After resuming from the L1 SLEEP state, the bit CTRLB.SOFE is set, allowing Start-of-Frame generation. © 2018 Microchip Technology Inc.
PAGE 813
SAM D21 Family USB – Universal Serial Bus 32.6.3.17 Host Interrupt Figure 32-10. Host Interrupt PINTFLAG7.STALL PINTENSET.STALL PINTFLAG7.PERR PINTENSET.PERR PINTFLAG7.TRFAIL PINTENSET.TRFAIL PIPE7 PINTFLAG7.TXSTP PINTSMRY PINT7 PINTENSET.TXSTP PINT6 PINTFLAG7.TRCPT1 PINTENSET.TRCPT1 PINTFLAG7.TRCPT0 PINTENSET.TRCPT0 USB PIPE Interrupt PINTFLAG0.STALL PINTENSET.STALL PINTFLAG0.PERR PINTENSET.PERR PINTFLAG0.TRFAIL PINTENSET.TRFAIL PINTFLAG0.TXSTP PIPE0 PINT1 PINT0 PINTENSET.TXSTP PINTFLAG0.
PAGE 814
SAM D21 Family USB – Universal Serial Bus 32.7 Register Summary The register mapping depends on the Operating Mode field in the Control A register (CTRLA.MODE). The register summary is detailed below. 32.7.1 Offset Common Device Summary Name Bit Pos. 0x00 CTRLA 7:0 0x01 Reserved 0x02 SYNCBUSY 7:0 0x03 QOSCTRL 7:0 0x0D FSMSTATUS 7:0 MODE RUNSTBY DQOS[1:0] 7:0 DESCADD[7:0] 0x25 15:8 DESCADD[15:8] 23:16 DESCADD[23:16] DESCADD 0x27 31:24 0x28 7:0 0x29 32.7.
PAGE 815
SAM D21 Family USB – Universal Serial Bus ...........continued Offset 0x1C 0x1D Name INTFLAG 0x1E Reserved 0x1F Reserved 0x20 0x21 EPINTSMRY 0x22 Reserved 0x23 Reserved Bit Pos. 7:0 RAMACER UPRSM EORSM WAKEUP EORST SOF 15:8 SUSPEND LPMSUSP 7:0 EPINT[7:0] 15:8 EPINT[15:8] LPMNYET Table 32-2. Device Endpoint Register n Offset Name Bit Pos.
PAGE 816
SAM D21 Family USB – Universal Serial Bus Table 32-4. Device Endpoint n Descriptor Bank 1 Offset 0x Name Bit Pos. n0 + 0x10 + index 0x00 7:0 ADD[7:0] 0x01 15:8 ADD[15:8] 23:16 ADD[23:16] 0x02 ADDR 0x03 31:24 ADD[31:24] 0x04 7:0 BYTE_COUNT[7:0] 0x05 0x06 PCKSIZE 0x07 15:8 31:24 0x08 Reserved 7:0 0x09 Reserved 15:8 0x0A STATUS_BK 7:0 0x0B Reserved 7:0 0x0C Reserved 7:0 0x0D Reserved 7:0 0x0E Reserved 7:0 0x0F Reserved 7:0 32.7.
PAGE 817
SAM D21 Family USB – Universal Serial Bus ...........continued Offset Name 0x1A Reserved 0x1B Reserved 0x1C 0x1D INTFLAG 0x1E Reserved 0x1F Reserved 0x20 0x21 0x22 PINTSMRY Bit Pos. 7:0 RAMACER UPRSM DNRSM WAKEUP RST HSOF 15:8 DDISC 7:0 PINT[7:0] 15:8 PINT[15:8] DCONN Reserved 0x23 Table 32-6. Host Pipe Register n Offset Name Bit Pos.
PAGE 818
SAM D21 Family USB – Universal Serial Bus ...........continued Offset 0x Name Bit Pos. n0 + index 0x0E 0x0F STATUS_PIPE 7:0 ERCNT[2:0] CRC16ER TOUTER PIDER DAPIDER DTGLER 15:8 Table 32-8. Host Pipe n Descriptor Bank 1 Offset 0x Name Bit Pos.
PAGE 819
SAM D21 Family USB – Universal Serial Bus 32.8.1.1 Control A Name: Offset: Reset: Property: Bit Access Reset 7 CTRLA 0x00 0x00 PAC Write-Protection, Write-Synchronised 6 5 4 3 2 1 0 MODE RUNSTDBY ENABLE SWRST R/W R/W R/W R/W 0 0 0 0 Bit 7 – MODE Operating Mode This bit defines the operating mode of the USB. Value 0 1 Description USB Device mode USB Host mode Bit 2 – RUNSTDBY Run in Standby Mode This bit is Enable-Protected.
PAGE 820
SAM D21 Family USB – Universal Serial Bus Value 0 1 Description There is no reset operation ongoing. The reset operation is ongoing. © 2018 Microchip Technology Inc.
PAGE 821
SAM D21 Family USB – Universal Serial Bus 32.8.1.2 Synchronization Busy Name: Offset: Reset: Property: Bit 7 SYNCBUSY 0x02 0x00 - 6 5 4 3 2 1 0 ENABLE SWRST Access R R Reset 0 0 Bit 1 – ENABLE Synchronization Enable status bit This bit is cleared when the synchronization of ENABLE register between the clock domains is complete. This bit is set when the synchronization of ENABLE register between clock domains is started.
PAGE 822
SAM D21 Family USB – Universal Serial Bus 32.8.1.3 QOS Control Name: Offset: Reset: Property: Bit 7 QOSCTRL 0x03 0x05 PAC Write-Protection 6 5 4 3 2 1 R/W R/W R/W R/W 0 1 0 1 DQOS[1:0] Access Reset 0 CQOS[1:0] Bits 3:2 – DQOS[1:0] Data Quality of Service These bits define the memory priority access during the endpoint or pipe read/write data operation. Refer to SRAM Quality of Service.
PAGE 823
SAM D21 Family USB – Universal Serial Bus 32.8.1.4 Finite State Machine Status Name: Offset: Reset: Property: Bit 7 FSMSTATUS 0x0D 0xXXXX Read only 6 5 4 Access R R R Reset 0 0 0 3 2 1 0 R R R R 0 0 0 1 FSMSTATE[6:0] Bits 6:0 – FSMSTATE[6:0] Fine State Machine Status These bits indicate the state of the finite state machine of the USB controller.
PAGE 824
SAM D21 Family USB – Universal Serial Bus 32.8.1.
PAGE 825
SAM D21 Family USB – Universal Serial Bus 32.8.1.6 Pad Calibration Name: Offset: Reset: Property: PADCAL 0x28 0x0000 PAC Write-Protection The Pad Calibration values must be loaded from the NVM Software Calibration Area into the USB Pad Calibration register by software, before enabling the USB, to achieve the specified accuracy. Refer to NVM Software Calibration Area Mapping for further details. Refer to for further details.
PAGE 826
SAM D21 Family USB – Universal Serial Bus 32.8.2.1 Control B Name: Offset: Reset: Property: Bit 15 CTRLB 0x08 0x0000 PAC Write-Protection 14 13 12 11 10 LPMHDSK[1:0] Access Reset Bit 7 6 5 4 9 GNAK R/W R/W R/W 0 0 0 3 2 NREPLY SPDCONF[1:0] 8 1 0 UPRSM DETACH Access R R/W R/W R/W R/W Reset 0 0 0 0 0 Bits 11:10 – LPMHDSK[1:0] Link Power Management Handshake These bits select the Link Power Management Handshake configuration.
PAGE 827
SAM D21 Family USB – Universal Serial Bus Value 0x0 0x1 0x2 0x3 Description FS: Full-speed LS: Low-speed Reserved Reserved Bit 1 – UPRSM Upstream Resume This bit is cleared when the USB receives a USB reset or once the upstream resume has been sent. Value 0 1 Description Writing a zero to this bit has no effect. Writing a one to this bit will generate an upstream resume to the host for a remote wakeup.
PAGE 828
SAM D21 Family USB – Universal Serial Bus 32.8.2.2 Device Address Name: Offset: Reset: Property: Bit 7 DADD 0x0A 0x00 PAC Write-Protection 6 5 4 R/W R/W R/W R/W 0 0 0 0 ADDEN Access Reset 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 DADD[6:0] Bit 7 – ADDEN Device Address Enable This bit is cleared when a USB reset is received. Value 0 1 Description Writing a zero will deactivate the DADD field (USB device address) and return the device to default address 0.
PAGE 829
SAM D21 Family USB – Universal Serial Bus 32.8.2.3 Status Name: Offset: Reset: Property: STATUS 0x0C 0x40 - Bit 7 6 5 4 3 Access R R R/W R/W Reset 0 1 0 1 LINESTATE[1:0] 2 1 0 SPEED[1:0] Bits 7:6 – LINESTATE[1:0] USB Line State Status These bits define the current line state DP/DM. LINESTATE[1:0] USB Line Status 0x0 SE0/RESET 0x1 FS-J or LS-K State 0x2 FS-K or LS-J State Bits 3:2 – SPEED[1:0] Speed Status These bits define the current speed used of the device .
PAGE 830
SAM D21 Family USB – Universal Serial Bus 32.8.2.4 Device Frame Number Name: Offset: Reset: Property: Bit 15 FNUM 0x10 0x0000 Read only 14 13 12 11 10 9 8 R/W R/W R/W R/W Reset 0 0 R/W R/W R/W 0 0 0 0 0 Bit 7 5 4 3 2 1 0 FNCERR Access FNUM[10:5] 6 FNUM[4:0] Access Reset MFNUM[2:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 15 – FNCERR Frame Number CRC Error This bit is cleared upon receiving a USB reset.
PAGE 831
SAM D21 Family USB – Universal Serial Bus 32.8.2.5 Device Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x14 0x0000 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
PAGE 832
SAM D21 Family USB – Universal Serial Bus Bit 6 – UPRSM Upstream Resume Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding interrupt request. Value 0 1 Description The Upstream Resume interrupt is disabled. The Upstream Resume interrupt is enabled and an interrupt request will be generated when the Upstream Resume interrupt Flag is set.
PAGE 833
SAM D21 Family USB – Universal Serial Bus Bit 0 – SUSPEND Suspend Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the Suspend Interrupt Enable bit and disable the corresponding interrupt request. Value 0 1 Description The Suspend interrupt is disabled. The Suspend interrupt is enabled and an interrupt request will be generated when the Suspend interrupt Flag is set. © 2018 Microchip Technology Inc.
PAGE 834
SAM D21 Family USB – Universal Serial Bus 32.8.2.6 Device Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x18 0x0000 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
PAGE 835
SAM D21 Family USB – Universal Serial Bus Writing a one to this bit will set the Upstream Resume Enable bit and enable the corresponding interrupt request. Value 0 1 Description The Upstream Resume interrupt is disabled. The Upstream Resume interrupt is enabled. Bit 5 – EORSM End Of Resume Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the End Of Resume interrupt Enable bit and enable the corresponding interrupt request.
PAGE 836
SAM D21 Family USB – Universal Serial Bus Value 0 1 Description The Suspend interrupt is disabled. The Suspend interrupt is enabled. © 2018 Microchip Technology Inc.
PAGE 837
SAM D21 Family USB – Universal Serial Bus 32.8.2.7 Device Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 15 INTFLAG 0x01C 0x0000 - 14 13 12 11 10 Access Reset Bit Access Reset 9 8 LPMSUSP LPMNYET R/W R/W 0 0 7 6 5 4 3 2 RAMACER UPRSM EORSM WAKEUP EORST SOF 1 SUSPEND 0 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Bit 9 – LPMSUSP Link Power Management Suspend Interrupt Flag This flag is cleared by writing a one to the flag.
PAGE 838
SAM D21 Family USB – Universal Serial Bus Bit 5 – EORSM End Of Resume Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when the USB detects a valid “End of Resume” signal initiated by the host and will generate an interrupt if INTENCLR/SET.EORSM is one. Writing a zero to this bit has no effect. Bit 4 – WAKEUP Wake Up Interrupt Flag This flag is cleared by writing a one to the flag.
PAGE 839
SAM D21 Family USB – Universal Serial Bus 32.8.2.8 Endpoint Interrupt Summary Name: Offset: Reset: Property: EPINTSMRY 0x20 0x0000 - Bit 15 14 13 12 11 10 9 8 Access R R R R Reset 0 0 R R R R 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EPINT[15:8] EPINT[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15:0 – EPINT[15:0] EndPoint Interrupt The flag EPINT[n] is set when an interrupt is triggered by the EndPoint n. See 32.8.3.
PAGE 840
SAM D21 Family USB – Universal Serial Bus 32.8.3.1 Device Endpoint Configuration register n Name: Offset: Reset: Property: Bit 7 EPCFGn 0x100 + (n x 0x20) 0x00 PAC Write-Protection 6 5 4 3 2 EPTYPE1[2:0] Access Reset 1 0 EPTYPE0[2:0] R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 6:4 – EPTYPE1[2:0] Endpoint Type for IN direction These bits contains the endpoint type for IN direction. Upon receiving a USB reset EPCFGn.EPTYPE1 is cleared except for endpoint 0 which is unchanged.
PAGE 841
SAM D21 Family USB – Universal Serial Bus 32.8.3.2 EndPoint Status Clear n Name: Offset: Reset: Property: Bit EPSTATUSCLRn 0x104 + (n * 0x20) 0x00 PAC Write-Protection 7 6 5 4 3 2 1 0 BK1RDY BK0RDY STALLRQ1 STALLRQ0 CURBK DTGLIN DTGLOUT Access W W W W W W W Reset 0 0 0 0 0 0 0 Bit 7 – BK1RDY Bank 1 Ready Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear EPSTATUS.BK1RDY bit.
PAGE 842
SAM D21 Family USB – Universal Serial Bus 32.8.3.3 EndPoint Status Set n Name: Offset: Reset: Property: Bit EPSTATUSSETn 0x105 + (n x 0x20) 0x00 PAC Write-Protection 7 6 5 4 3 2 1 0 BK1RDY BK0RDY STALLRQ1 STALLRQ0 CURBK DTGLIN DTGLOUT Access W W W W W W W Reset 0 0 0 0 0 0 0 Bit 7 – BK1RDY Bank 1 Ready Set Writing a zero to this bit has no effect. Writing a one to this bit will set EPSTATUS.BK1RDY bit.
PAGE 843
SAM D21 Family USB – Universal Serial Bus 32.8.3.4 EndPoint Status n Name: Offset: Reset: Property: Bit EPSTATUSn 0x106 + (n x 0x20) 0x00 PAC Write-Protection 7 6 5 4 3 2 1 0 BK1RDY BK0RDY STALLRQ CURBK DTGLIN DTGLOUT Access R R R R R R Reset 0 0 2 0 0 0 Bit 7 – BK1RDY Bank 1 is ready For Control/OUT direction Endpoints, the bank is empty. Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit. Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit.
PAGE 844
SAM D21 Family USB – Universal Serial Bus Value 1 Description The bank1 is the bank that will be used in the next single/multi USB packet. Bit 1 – DTGLIN Data Toggle IN Sequence Writing a zero to the bit EPSTATUSCLR.DTGLINCLR will clear this bit. Writing a one to the bit EPSTATUSSET.DTGLINSET will set this bit. Value 0 1 Description The PID of the next expected IN transaction will be zero: data 0. The PID of the next expected IN transaction will be one: data 1.
PAGE 845
SAM D21 Family USB – Universal Serial Bus 32.8.3.5 Device EndPoint Interrupt Flag n Name: Offset: Reset: Property: Bit 7 EPINTFLAGn 0x107 + (n x 0x20) 0x00 - 6 Access Reset 5 4 3 2 1 0 STALL RXSTP TRFAIL TRCPT R/W R/W R/W R/W 0 0 0 0 Bit 5 – STALL Transmit Stall x Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a Transmit Stall occurs and will generate an interrupt if EPINTENCLR/SET.STALL is one. EPINTFLAG.
PAGE 846
SAM D21 Family USB – Universal Serial Bus Writing a zero to this bit has no effect. Writing a one to this bit clears the TRCPT0 Interrupt Flag. © 2018 Microchip Technology Inc.
PAGE 847
SAM D21 Family USB – Universal Serial Bus 32.8.3.6 Device EndPoint Interrupt Enable n Name: Offset: Reset: Property: EPINTENCLRn 0x108 + (n x 0x20) 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENSET) register.
PAGE 848
SAM D21 Family USB – Universal Serial Bus Writing a one to this bit will clear the Transfer Complete x interrupt Enable bit and disable the corresponding interrupt request. Value 0 1 Description The Transfer Complete bank x interrupt is disabled. The Transfer Complete bank x interrupt is enabled and an interrupt request will be generated when the Transfer Complete x Interrupt Flag is set. © 2018 Microchip Technology Inc.
PAGE 849
SAM D21 Family USB – Universal Serial Bus 32.8.3.7 Device Interrupt EndPoint Set n Name: Offset: Reset: Property: EPINTENSETn 0x109 + (n x 0x20) 0x0000 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENCLR) register. This register is cleared by USB reset or when EPEN[n] is zero.
PAGE 850
SAM D21 Family USB – Universal Serial Bus 32.8.4 Device Registers - Endpoint RAM 32.8.4.1 Endpoint Descriptor Structure Data Buffers EPn BK1 EPn BK0 Endpoint descriptors Reserved Bank1 Reserved PCKSIZE ADDR (2 x 0xn0) + 0x10 Reserved STATUS_BK Bank0 EXTREG PCKSIZE ADDR 2 x 0xn0 Reserved +0x01B +0x01A +0x018 +0x014 +0x010 +0x00B +0x00A +0x008 +0x004 +0x000 STATUS_BK Descriptor E0 Bank1 Reserved PCKSIZE ADDR Bank0 Reserved STATUS_BK EXTREG PCKSIZE ADDR © 2018 Microchip Technology Inc.
PAGE 851
SAM D21 Family USB – Universal Serial Bus 32.8.4.
PAGE 852
SAM D21 Family USB – Universal Serial Bus 32.8.4.
PAGE 853
SAM D21 Family USB – Universal Serial Bus ...........continued Value Description 0x5 256 Byte(1) 0x6 512 Byte(1) 0x7 1023 Byte(1) (1) for Isochronous endpoints only. Bits 27:14 – MULTI_PACKET_SIZE[13:0] Multiple Packet Size These bits define the 14-bit value that is used for multi-packet transfers. For IN endpoints, MULTI_PACKET_SIZE holds the total number of bytes sent. MULTI_PACKET_SIZE should be written to zero when setting up a new transfer.
PAGE 854
SAM D21 Family USB – Universal Serial Bus 32.8.4.
PAGE 855
SAM D21 Family USB – Universal Serial Bus 32.8.4.5 Device Status Bank Name: Offset: Reset: Property: Bit 7 STATUS_BK 0x0A & 0x1A 0xxxxxxxx NA 6 5 4 3 Access Reset 2 1 0 ERRORFLOW CRCERR R/W R/W x x Bit 1 – ERRORFLOW Error Flow Status This bit defines the Error Flow Status. This bit is set when a Error Flow has been detected during transfer from/towards this bank. For OUT transfer, a NAK handshake has been sent. For Isochronous OUT transfer, an overrun condition has occurred.
PAGE 856
SAM D21 Family USB – Universal Serial Bus 32.8.5.1 Control B Name: Offset: Reset: Property: Bit 15 CTRLB 0x08 0x0000 PAC Write-Protection 14 13 12 Access Reset Bit 7 6 5 4 11 10 9 8 L1RESUME VBUSOK BUSRESET SOFE R/W R/W R/W R/W 0 0 0 0 3 2 1 0 SPDCONF[1:0] Access Reset RESUME R/W R/W R/W 0 0 0 Bit 11 – L1RESUME Send USB L1 Resume Writing 0 to this bit has no effect. 1: Generates a USB L1 Resume on the USB bus.
PAGE 857
SAM D21 Family USB – Universal Serial Bus Bits 3:2 – SPDCONF[1:0] Speed Configuration for Host These bits select the host speed configuration as shown below Value 0x0 0x1 0x2 0x3 Description Low and Full Speed capable Reserved Reserved Reserved Bit 1 – RESUME Send USB Resume Writing 0 to this bit has no effect. 1: Generates a USB Resume on the USB bus. This bit is cleared when the USB Resume has been sent or when a USB reset is requested. © 2018 Microchip Technology Inc.
PAGE 858
SAM D21 Family USB – Universal Serial Bus 32.8.5.2 Host Start-of-Frame Control Name: Offset: Reset: Property: HSOFC 0x0A 0x00 PAC Write-Protection During a very short period just before transmitting a Start-of-Frame, this register is locked. Thus, after writing, it is recommended to check the register value, and write this register again if necessary. This register is cleared upon a USB reset.
PAGE 859
SAM D21 Family USB – Universal Serial Bus 32.8.5.3 Status Name: Offset: Reset: Property: STATUS 0x0C 0x00 Read only Bit 7 6 5 4 3 Access R R R/W R/W Reset 0 0 0 0 LINESTATE[1:0] 2 1 0 SPEED[1:0] Bits 7:6 – LINESTATE[1:0] USB Line State Status These bits define the current line state DP/DM. LINESTATE[1:0] USB Line Status 0x0 SE0/RESET 0x1 FS-J or LS-K State 0x2 FS-K or LS-J State Bits 3:2 – SPEED[1:0] Speed Status These bits define the current speed used by the host.
PAGE 860
SAM D21 Family USB – Universal Serial Bus 32.8.5.4 Host Frame Number Name: Offset: Reset: Property: Bit 15 FNUM 0x10 0x0000 PAC Write-Protection 14 13 12 11 10 9 8 R/W R/W R/W 0 R/W R/W R/W 0 0 0 0 0 5 4 3 2 1 0 FNUM[10:5] Access Reset Bit 7 6 FNUM[4:0] Access Reset R/W R/W R/W R/W R/W 0 0 0 0 0 Bits 13:3 – FNUM[10:0] Frame Number These bits contains the current SOF number. These bits can be written by software to initialize a new frame number value.
PAGE 861
SAM D21 Family USB – Universal Serial Bus 32.8.5.5 Host Frame Length Name: Offset: Reset: Property: FLENHIGH 0x12 0x00 Read-Only Bit 7 6 5 4 Access R R R R Reset 0 0 0 0 3 2 1 0 R R R R 0 0 0 0 FLENHIGH[7:0] Bits 7:0 – FLENHIGH[7:0] Frame Length These bits contains the 8 high-order bits of the internal frame counter. Table 32-9. Counter Description vs. Speed Host Register Description STATUS.
PAGE 862
SAM D21 Family USB – Universal Serial Bus 32.8.5.6 Host Interrupt Enable Register Clear Name: Offset: Reset: Property: INTENCLR 0x14 0x0000 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
PAGE 863
SAM D21 Family USB – Universal Serial Bus Bit 6 – UPRSM Upstream Resume from Device Interrupt Disable Writing a zero to this bit has no effect. Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding interrupt request. Value 0 1 Description The Upstream Resume interrupt is disabled. The Upstream Resume interrupt is enabled and an interrupt request will be generated when the Upstream Resume interrupt Flag is set.
PAGE 864
SAM D21 Family USB – Universal Serial Bus 32.8.5.7 Host Interrupt Enable Register Set Name: Offset: Reset: Property: INTENSET 0x18 0x0000 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
PAGE 865
SAM D21 Family USB – Universal Serial Bus Value 0 1 Description The Upstream Resume interrupt is disabled. The Upstream Resume interrupt is enabled. Bit 5 – DNRSM Down Resume Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the Down Resume interrupt Enable bit and enable the DNRSM interrupt. Value 0 1 Description The Down Resume interrupt is disabled. The Down Resume interrupt is enabled.
PAGE 866
SAM D21 Family USB – Universal Serial Bus 32.8.5.8 Host Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 15 INTFLAG 0x1C 0x0000 - 14 13 12 11 10 Access Reset Bit Access Reset 7 6 5 4 3 2 RAMACER UPRSM DNRSM WAKEUP RST HSOF R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 9 8 DDISC DCONN R/W R/W 0 0 1 0 Bit 9 – DDISC Device Disconnection Interrupt Flag This flag is cleared by writing a one to the flag.
PAGE 867
SAM D21 Family USB – Universal Serial Bus Bit 5 – DNRSM Down Resume Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when the USB has sent a Down Resume and will generate an interrupt if INTENCLR/ SET.DRSM is one. Writing a zero to this bit has no effect. Bit 4 – WAKEUP Wake Up Interrupt Flag This flag is cleared by writing a one. This flag is set when: l The host controller is in suspend mode (SOFE is zero) and an upstream resume from the device is detected.
PAGE 868
SAM D21 Family USB – Universal Serial Bus 32.8.5.9 Pipe Interrupt Summary Name: Offset: Reset: Property: PINTSMRY 0x20 0x0000 Read-only Bit 15 14 13 12 11 10 9 8 Access R R R R Reset 0 0 R R R R 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PINT[15:8] PINT[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15:0 – PINT[15:0] The flag PINT[n] is set when an interrupt is triggered by the pipe n. See 32.8.6.6 PINTFLAG register in the Host Pipe Register section.
PAGE 869
SAM D21 Family USB – Universal Serial Bus 32.8.6.1 Host Pipe n Configuration Name: Offset: Reset: Property: Bit PCFGn 0x100 + (n x 0x20) 0x00 PAC Write-Protection 7 6 5 4 3 2 PTYPE[2:0] Access Reset 1 BK 0 PTOKEN[1:0] R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 5:3 – PTYPE[2:0] Type of the Pipe These bits contains the pipe type.
PAGE 870
SAM D21 Family USB – Universal Serial Bus PTOKEN[1:0](1) Description 0x0 SETUP(2) 0x1 IN 0x2 OUT 0x3 Reserved 1. 2. PTOKEN field is ignored when PTYPE is configured as EXTENDED. Available only when PTYPE is configured as CONTROL Theses bits are cleared upon sending a USB reset. © 2018 Microchip Technology Inc.
PAGE 871
SAM D21 Family USB – Universal Serial Bus 32.8.6.2 Interval for the Bulk-Out/Ping Transaction Name: Offset: Reset: Property: Bit BINTERVAL 0x103 + (n x 0x20) 0x00 PAC Write-Protection 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 BINTERVAL[7:0] Access Reset Bits 7:0 – BINTERVAL[7:0] BINTERVAL These bits contains the Ping/Bulk-out period. These bits are cleared when a USB reset is sent or when PEN[n] is zero.
PAGE 872
SAM D21 Family USB – Universal Serial Bus 32.8.6.3 Pipe Status Clear n Name: Offset: Reset: Property: Bit PSTATUSCLR 0x104 + (n x 0x20) 0x00 PAC Write-Protection 7 6 5 4 3 2 1 0 BK1RDY BK0RDY PFREEZE CURBK DTGL Access W W W W W Reset 0 0 0 0 0 Bit 7 – BK1RDY Bank 1 Ready Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear PSTATUS.BK1RDY bit. Bit 6 – BK0RDY Bank 0 Ready Clear Writing a zero to this bit has no effect.
PAGE 873
SAM D21 Family USB – Universal Serial Bus 32.8.6.4 Pipe Status Set Register n Name: Offset: Reset: Property: Bit PSTATUSSET 0x105 + (n x 0x20) 0x00 PAC Write-Protection 7 6 5 4 3 2 1 0 BK1RDY BK0RDY PFREEZE CURBK DTGL Access W W W W W Reset 0 0 0 0 0 Bit 7 – BK1RDY Bank 1 Ready Set Writing a zero to this bit has no effect. Writing a one to this bit will set the bit PSTATUS.BK1RDY. Bit 6 – BK0RDY Bank 0 Ready Set Writing a zero to this bit has no effect.
PAGE 874
SAM D21 Family USB – Universal Serial Bus 32.8.6.5 Pipe Status Register n Name: Offset: Reset: Property: Bit PSTATUS 0x106 + (n x 0x20) 0x00 PAC Write-Protection 7 6 5 4 3 2 1 0 BK1RDY BK0RDY PFREEZE CURBK DTGL Access R R R R R Reset 0 0 0 0 0 Bit 7 – BK1RDY Bank 1 is ready Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit. Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit. This bank is not used for Control pipe.
PAGE 875
SAM D21 Family USB – Universal Serial Bus When PFREEZE bit is set while a transaction is in progress on the USB bus, this transaction will be properly completed. PFREEZE bit will be read as “1” only when the ongoing transaction will have been completed. Value 0 1 Description The Pipe operates in normal operation. The Pipe is frozen and no additional requests will be sent to the device on this pipe address.
PAGE 876
SAM D21 Family USB – Universal Serial Bus 32.8.6.6 Host Pipe Interrupt Flag Register Name: Offset: Reset: Property: Bit 7 PINTFLAG 0x107 + (n x 0x20) 0x00 - 6 Access Reset 5 4 3 2 1 0 STALL TXSTP PERR TRFAIL TRCPT R/W R/W R/W R/W R/W 0 0 0 0 2 Bit 5 – STALL STALL Received Interrupt Flag This flag is cleared by writing a one to the flag. This flag is set when a stall occurs and will generate an interrupt if PINTENCLR/SET.STALL is one. Writing a zero to this bit has no effect.
PAGE 877
SAM D21 Family USB – Universal Serial Bus Writing a zero to this bit has no effect. Writing a one to this bit clears the TRCPT Interrupt Flag. © 2018 Microchip Technology Inc.
PAGE 878
SAM D21 Family USB – Universal Serial Bus 32.8.6.7 Host Pipe Interrupt Clear Register Name: Offset: Reset: Property: PINTENCLR 0x108 + (n x 0x20) 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Pipe Interrupt Enable Set (PINTENSET) register. This register is cleared by USB reset or when PEN[n] is zero.
PAGE 879
SAM D21 Family USB – Universal Serial Bus Writing a one to this bit will clear the Transfer Fail interrupt Enable bit and disable the corresponding interrupt request. Value 0 1 Description The Transfer Fail interrupt is disabled. The Transfer Fail interrupt is enabled and an interrupt request will be generated when the Transfer Fail interrupt Flag is set. Bit 0 – TRCPT Transfer Complete Bank x interrupt Disable Writing a zero to this bit has no effect.
PAGE 880
SAM D21 Family USB – Universal Serial Bus 32.8.6.8 Host Interrupt Pipe Set Register Name: Offset: Reset: Property: PINTENSET 0x109 + (n x 0x20) 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Pipe Interrupt Enable Set (PINTENCLR) register. This register is cleared by USB reset or when PEN[n] is zero.
PAGE 881
SAM D21 Family USB – Universal Serial Bus Bit 0 – TRCPT Transfer Complete x interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will enable the Transfer Complete interrupt Enable bit x. 0.2.7 Host Registers - Pipe RAM Value 0 1 Description The Transfer Complete x interrupt is disabled. The Transfer Complete x interrupt is enabled. © 2018 Microchip Technology Inc.
PAGE 882
SAM D21 Family USB – Universal Serial Bus 32.8.7 Host Registers - Pipe RAM 32.8.7.
PAGE 883
SAM D21 Family USB – Universal Serial Bus 32.8.7.
PAGE 884
SAM D21 Family USB – Universal Serial Bus 32.8.7.
PAGE 885
SAM D21 Family USB – Universal Serial Bus ...........continued SIZE[2:0] Description 0x4 128 Byte(1) 0x5 256 Byte(1) 0x6 512 Byte(1) 0x7 1024 Byte in HS mode(1) 1023 Byte in FS mode(1) 1. For Isochronous pipe only. Bits 27:14 – MULTI_PACKET_SIZE[13:0] Multi Packet IN or OUT size These bits define the 14-bit value that is used for multi-packet transfers. For IN pipes, MULTI_PACKET_SIZE holds the total number of bytes sent. MULTI_PACKET_SIZE should be written to zero when setting up a new transfer.
PAGE 886
SAM D21 Family USB – Universal Serial Bus 32.8.7.4 Extended Register Name: Offset: Reset: Property: Bit EXTREG 0x08 0xxxxxxxx NA 15 14 13 12 R/W R/W R/W 0 0 0 6 5 4 11 10 9 8 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 VARIABLE[10:4] Access Reset Bit 7 VARIABLE[3:0] Access Reset SUBPID[3:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 x 0 0 0 x Bits 14:4 – VARIABLE[10:0] Variable field send with extended token These bits define the VARIABLE field sent with extended token.
PAGE 887
SAM D21 Family USB – Universal Serial Bus 32.8.7.5 Host Status Bank Name: Offset: Reset: Property: Bit 7 STATUS_BK 0x0A & 0x1A 0xxxxxxxx NA 6 5 4 3 Access Reset 2 1 0 ERRORFLOW CRCERR R/W R/W x x Bit 1 – ERRORFLOW Error Flow Status This bit defines the Error Flow Status. This bit is set when a Error Flow has been detected during transfer from/towards this bank. For IN transfer, a NAK handshake has been received. For OUT transfer, a NAK handshake has been received.
PAGE 888
SAM D21 Family USB – Universal Serial Bus 32.8.7.
PAGE 889
SAM D21 Family USB – Universal Serial Bus 32.8.7.7 Host Status Pipe Name: Offset: Reset: Property: Bit 15 STATUS_PIPE 0x0E & 0x1E 0xxxxxxxx PAC Write-Protection, Write-Synchronized, Read-Synchronized 14 13 6 5 12 11 10 9 8 Access Reset Bit 7 ERCNT[2:0] Access Reset 4 3 2 1 0 CRC16ER TOUTER PIDER DAPIDER DTGLER R/W R/W R/W R/W R/W R/W R/W R/W 0 0 x x x x x x Bits 7:5 – ERCNT[2:0] Pipe Error Counter These bits define the number of errors detected on the pipe.
PAGE 890
SAM D21 Family USB – Universal Serial Bus Value 0 1 Description No Data PID Error detected. A Data PID error has been detected. Bit 0 – DTGLER Data Toggle Error This bit defines the Data Toggle Error Status. This bit is set when a Data Toggle Error has been detected. Value 0 1 Description No Data Toggle Error. Data Toggle Error detected. © 2018 Microchip Technology Inc.
PAGE 891
SAM D21 Family ADC – Analog-to-Digital Converter 33. 33.1 ADC – Analog-to-Digital Converter Overview The Analog-to-Digital Converter (ADC) converts analog signals to digital values. The ADC has 12-bit resolution, and is capable of converting up to 350ksps. The input selection is flexible, and both differential and single-ended measurements can be performed. An optional gain stage is available to increase the dynamic range. In addition, several internal signal inputs are available.
PAGE 892
SAM D21 Family ADC – Analog-to-Digital Converter • • • • • 33.3 – Four bits for reference selection Event-triggered conversion for accurate timing (one event input) Optional DMA transfer of conversion result Hardware gain and offset compensation Averaging and oversampling with decimation to support, up to 16-bit result Selectable sampling time Block Diagram Figure 33-1. ADC Block Diagram CTRLA WINCTRL AVGCTRL WINLT SAMPCTRL WINUT EVCTRL OFFSETCORR SWTRIG GAINCORR INPUTCTRL ADC0 ... ADCn INT.
PAGE 893
SAM D21 Family ADC – Analog-to-Digital Converter Note: Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be mapped on several pins. Related Links 7. I/O Multiplexing and Considerations 2. Configuration Summary 33.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 33.5.
PAGE 894
SAM D21 Family ADC – Analog-to-Digital Converter 11.2 Nested Vector Interrupt Controller 33.5.6 Events The events are connected to the Event System. Related Links 24. EVSYS – Event System 33.5.7 Debug Operation When the CPU is halted in debug mode the ADC will halt normal operation. The ADC can be forced to continue operation during debugging. 33.5.
PAGE 895
SAM D21 Family ADC – Analog-to-Digital Converter other configuration registers must be stable during the conversion. The source for GCLK_ADC is selected and enabled in the System Controller (SYSCTRL). Refer to SYSCTRL – System Controller for more details. When GCLK_ADC is enabled, the ADC can be enabled by writing a one to the Enable bit in the Control Register A (CTRLA.ENABLE). Related Links 17. SYSCTRL – System Controller 33.6.2.
PAGE 896
SAM D21 Family ADC – Analog-to-Digital Converter Figure 33-2. ADC Prescaler DIV512 DIV256 DIV128 DIV64 DIV32 DIV8 DIV16 9-BIT PRESCALER DIV4 GCLK_ADC CTRLB.PRESCALER[2:0] CLK_ADC The propagation delay of an ADC measurement depends on the selected mode and is given by: • Single-shot mode: • PropagationDelay = Free-running mode: 1+ PropagationDelay = Table 33-1.
PAGE 897
SAM D21 Family ADC – Analog-to-Digital Converter 33.6.5 Differential and Single-Ended Conversions The ADC has two conversion options: differential and single-ended: • If the positive input may go below the negative input, the differential mode should be used in order to get correct results. • If the positive input is always positive, the single-ended conversion should be used in order to have full 12-bit resolution in the conversion. The negative input must be connected to ground.
PAGE 898
SAM D21 Family ADC – Analog-to-Digital Converter Figure 33-4. ADC Timing for One Conversion in Differential Mode without Gain, but with Increased Sampling Time 1 2 3 4 5 6 7 8 9 10 11 CLK_ ADC START SAMPLE INT Converting Bit MS B 10 9 8 7 6 5 4 3 2 1 LS B Figure 33-5.
PAGE 899
SAM D21 Family ADC – Analog-to-Digital Converter 33.6.6 Accumulation The result from multiple consecutive conversions can be accumulated. The number of samples to be accumulated is specified by the Number of Samples to be Collected field in the Average Control register (AVGCTRL.SAMPLENUM). When accumulating more than 16 samples, the result will be too large to match the 16-bit RESULT register size. To avoid overflow, the result is right shifted automatically to fit within the available register size.
PAGE 900
SAM D21 Family ADC – Analog-to-Digital Converter Table 33-3. Averaging 33.6.8 Number of Accumulated Samples AVGCTRL. SAMPLENUM Intermediate Result Precision Number of Automatic Right Shifts Division Factor AVGCTRL.
PAGE 901
SAM D21 Family ADC – Analog-to-Digital Converter that e.g. in 8-bit mode, only the eight lower bits will be considered. In addition, in differential mode, the eighth bit will be considered as the sign bit, even if the ninth bit is zero. The INTFLAG.WINMON interrupt flag will be set if the conversion result matches the window monitor condition. 33.6.10 Offset and Gain Correction Inherent gain and offset errors affect the absolute accuracy of the ADC.
PAGE 902
SAM D21 Family ADC – Analog-to-Digital Converter • • Window Monitor: WINMON Overrun: OVERRUN Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs.
PAGE 903
SAM D21 Family ADC – Analog-to-Digital Converter When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization Ready interrupt can be used to signal when synchronization is complete. If an operation that requires synchronization is executed while STATUS.SYNCBUSY=1, the bus will be stalled.
PAGE 904
SAM D21 Family ADC – Analog-to-Digital Converter 33.7 Register Summary Offset Name Bit Pos. 0x00 CTRLA 7:0 0x01 REFCTRL 7:0 0x02 AVGCTRL 7:0 0x03 SAMPCTRL 7:0 0x04 CTRLB RUNSTDBY REFCOMP ENABLE SWRST REFSEL[3:0] ADJRES[2:0] SAMPLENUM[3:0] SAMPLEN[5:0] 7:0 RESSEL[1:0] CORREN FREERUN LEFTADJ 15:8 PRESCALER[2:0] 7:0 WINMODE[2:0] 7:0 START DIFFMODE 0x06 ... Reserved 0x07 0x08 WINCTRL 0x09 ... Reserved 0x0B 0x0C SWTRIG FLUSH 0x0D ...
PAGE 905
SAM D21 Family ADC – Analog-to-Digital Converter ...........continued Offset Name 0x28 CALIB 0x2A DBGCTRL 33.8 Bit Pos. 7:0 LINEARITY_CAL[7:0] 15:8 BIAS_CAL[2:0] 7:0 DBGRUN Register Description Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
PAGE 906
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.1 Control A Name: Offset: Reset: Property: Bit 7 CTRLA 0x00 0x00 Write-Protected 6 5 4 3 Access Reset 2 1 0 RUNSTDBY ENABLE SWRST R/W R/W R/W 0 0 0 Bit 2 – RUNSTDBY Run in Standby This bit indicates whether the ADC will continue running in standby sleep mode or not: Value 0 1 Description The ADC is halted during standby sleep mode. The ADC continues normal operation during standby sleep mode.
PAGE 907
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.2 Reference Control Name: Offset: Reset: Property: Bit REFCTRL 0x01 0x00 Write-Protected 7 6 5 4 3 2 REFCOMP Access Reset 1 0 REFSEL[3:0] R/W R/W R/W R/W R/W 0 0 0 0 0 Bit 7 – REFCOMP Reference Buffer Offset Compensation Enable The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference.
PAGE 908
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.3 Average Control Name: Offset: Reset: Property: Bit 7 AVGCTRL 0x02 0x00 Write-Protected 6 5 4 3 ADJRES[2:0] Access Reset 2 1 0 SAMPLENUM[3:0] R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Bits 6:4 – ADJRES[2:0] Adjusting Result / Division Coefficient These bits define the division coefficient in 2n steps. Bits 3:0 – SAMPLENUM[3:0] Number of Samples to be Collected These bits define how many samples should be added together.
PAGE 909
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.4 Sampling Time Control Name: Offset: Reset: Property: Bit 7 SAMPCTRL 0x03 0x00 Write-Protected 6 5 4 3 2 1 0 SAMPLEN[5:0] Access Reset R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 5:0 – SAMPLEN[5:0] Sampling Time Length These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance.
PAGE 910
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.5 Control B Name: Offset: Reset: Property: Bit CTRLB 0x04 0x0000 Write-Protected, Write-Synchronized 15 14 13 12 11 10 9 8 PRESCALER[2:0] Access Reset Bit 7 6 5 4 RESSEL[1:0] Access Reset R/W R/W R/W 0 0 0 3 2 1 0 CORREN FREERUN LEFTADJ DIFFMODE R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 10:8 – PRESCALER[2:0] Prescaler Configuration These bits define the ADC clock relative to the peripheral clock.
PAGE 911
SAM D21 Family ADC – Analog-to-Digital Converter Value 1 Description Enable the digital result correction. The ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. Conversion time will be increased by X cycles according to the value in the Offset Correction Value bit group in the Offset Correction register. Bit 2 – FREERUN Free Running Mode Value 0 1 Description The ADC run is single conversion mode.
PAGE 912
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.6 Window Monitor Control Name: Offset: Reset: Property: Bit WINCTRL 0x08 0x00 Write-Protected, Write-Synchronized 7 6 5 4 3 2 1 0 WINMODE[2:0] Access R/W R/W R/W 0 0 0 Reset Bits 2:0 – WINMODE[2:0] Window Monitor Mode These bits enable and define the window monitor mode.
PAGE 913
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.7 Software Trigger Name: Offset: Reset: Property: Bit 7 SWTRIG 0x0C 0x00 Write-Protected, Write-Synchronized 6 5 4 3 Access Reset 2 1 0 START FLUSH R/W R/W 0 0 Bit 1 – START ADC Start Conversion Writing this bit to zero will have no effect. Value 0 1 Description The ADC will not start a conversion. The ADC will start a conversion. The bit is cleared by hardware when the conversion has started.
PAGE 914
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.
PAGE 915
SAM D21 Family ADC – Analog-to-Digital Converter After a conversion, the INPUTOFFSET register will be incremented by one, causing the next conversion to be done with the positive input equal to MUXPOS + INPUTOFFSET. The sum of MUXPOS and INPUTOFFSET gives the input that is actually converted. Bits 19:16 – INPUTSCAN[3:0] Number of Input Channels Included in Scan This register gives the number of input sources included in the pin scan. The number of input sources included is INPUTSCAN + 1.
PAGE 916
SAM D21 Family ADC – Analog-to-Digital Converter ...........
PAGE 917
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.9 Event Control Name: Offset: Reset: Property: Bit 7 EVCTRL 0x14 0x00 Write-Protected 6 Access Reset 5 4 1 0 WINMONEO RESRDYEO 3 2 SYNCEI STARTEI R/W R/W R/W R/W 0 0 0 0 Bit 5 – WINMONEO Window Monitor Event Out This bit indicates whether the Window Monitor event output is enabled or not and an output event will be generated when the window monitor detects something.
PAGE 918
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.10 Interrupt Enable Clear Name: Offset: Reset: Property: Bit 7 INTENCLR 0x16 0x00 Write-Protected 6 5 4 Access Reset 3 2 1 0 SYNCRDY WINMON OVERRUN RESRDY R/W R/W R/W R/W 0 0 0 0 Bit 3 – SYNCRDY Synchronization Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and the corresponding interrupt request.
PAGE 919
SAM D21 Family ADC – Analog-to-Digital Converter Value 1 Description The Result Ready interrupt is enabled, and an interrupt request will be generated when the Result Ready interrupt flag is set. © 2018 Microchip Technology Inc.
PAGE 920
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.11 Interrupt Enable Set Name: Offset: Reset: Property: Bit 7 INTENSET 0x17 0x00 Write-Protected 6 5 4 Access Reset 3 2 1 0 SYNCRDY WINMON OVERRUN RESRDY R/W R/W R/W R/W 0 0 0 0 Bit 3 – SYNCRDY Synchronization Ready Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit, which enables the Synchronization Ready interrupt.
PAGE 921
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.12 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 INTFLAG 0x18 0x00 - 6 5 4 3 2 1 0 SYNCRDY WINMON OVERRUN RESRDY R/W R/W R/W R/W 0 0 0 0 Access Reset Bit 3 – SYNCRDY Synchronization Ready This flag is cleared by writing a one to the flag. This flag is set on a one-to-zero transition of the Synchronization Busy bit in the Status register (STATUS.
PAGE 922
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.13 Status Name: Offset: Reset: Property: Bit 7 STATUS 0x19 0x00 - 6 5 4 3 2 1 0 SYNCBUSY Access R Reset 0 Bit 7 – SYNCBUSY Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. © 2018 Microchip Technology Inc.
PAGE 923
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.14 Result Name: Offset: Reset: Property: Bit 15 RESULT 0x1A 0x0000 Read-Synchronized 14 13 12 11 10 9 8 RESULT[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RESULT[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15:0 – RESULT[15:0] Result Conversion Value These bits will hold up to a 16-bit ADC result, depending on the configuration.
PAGE 924
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.
PAGE 925
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.
PAGE 926
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.17 Gain Correction Name: Offset: Reset: Property: Bit 15 GAINCORR 0x24 0x0000 Write-Protected 14 13 12 11 10 9 8 GAINCORR[11:8] Access Reset Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 GAINCORR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 11:0 – GAINCORR[11:0] Gain Correction Value If the CTRLB.
PAGE 927
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.18 Offset Correction Name: Offset: Reset: Property: Bit 15 OFFSETCORR 0x26 0x0000 Write-Protected 14 13 12 11 10 9 8 OFFSETCORR[11:8] Access Reset Bit 7 6 5 4 R/W R/W R/W R/W 0 0 0 0 3 2 1 0 OFFSETCORR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 11:0 – OFFSETCORR[11:0] Offset Correction Value If the CTRLB.
PAGE 928
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.
PAGE 929
SAM D21 Family ADC – Analog-to-Digital Converter 33.8.20 Debug Control Name: Offset: Reset: Property: Bit 7 DBGCTRL 0x2A 0x00 Write-Protected 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run This bit can be changed only while the ADC is disabled. This bit should be written only while a conversion is not ongoing. Value 0 1 Description The ADC is halted during debug mode. The ADC continues normal operation during debug mode. © 2018 Microchip Technology Inc.
PAGE 930
SAM D21 Family AC – Analog Comparators 34. 34.1 AC – Analog Comparators Overview The Analog Comparator (AC) supports multiple individual comparators. Each comparator (COMP) compares the voltage levels on two inputs, and provides a digital output based on this comparison. Each comparator may be configured to generate interrupt requests and/or peripheral events upon several different combinations of input change. Hysteresis can be adjusted to achieve the optimal operation for each application.
PAGE 931
SAM D21 Family AC – Analog Comparators 34.3 Block Diagram Figure 34-1. Analog Comparator Block Diagram (First Pair) AIN0 + AIN1 VDD SCALER - HYSTERESIS ENABLE DAC INTERRUPTS INTERRUPT MODE COMPCTRLn WINCTRL ENABLE BANDGAP AIN2 CMP0 COMP0 INTERRUPT SENSITIVITY CONTROL & WINDOW FUNCTION GCLK_AC HYSTERESIS + CMP1 COMP1 AIN3 EVENTS - Figure 34-2.
PAGE 932
SAM D21 Family AC – Analog Comparators 34.4 Signal Description Signal Description Type AIN[7..0] Analog input Comparator inputs CMP[2..0] Digital output Comparator outputs Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be mapped on several pins. Related Links 7. I/O Multiplexing and Considerations 34.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below.
PAGE 933
SAM D21 Family AC – Analog Comparators 34.5.5 Interrupts The interrupt request lines are connected to the interrupt controller. Using the AC interrupts requires the interrupt controller to be configured first. Refer to Nested Vector Interrupt Controller for details. Related Links 11.2 Nested Vector Interrupt Controller 34.5.6 Events The events are connected to the Event System. Refer to EVSYS – Event System for details on how to configure the Event System. Related Links 24. EVSYS – Event System 34.5.
PAGE 934
SAM D21 Family AC – Analog Comparators The individual comparators can be used independently (normal mode) or paired to form a window comparison (window mode). 34.6.2 Basic Operation 34.6.2.1 Initialization Before enabling the AC, the input and output events must be configured in the Event Control register (EVCTRL). These settings cannot be changed while the AC is enabled. 34.6.2.2 Enabling, Disabling and Resetting The AC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.
PAGE 935
SAM D21 Family AC – Analog Comparators supply level, and is specified in Electrical Characteristics. During the start-up time, the COMP output is not available. The comparator can be configured to generate interrupts when the output toggles, when the output changes from '0' to '1' (rising edge), when the output changes from '1' to '0' (falling edge) or at the end of the comparison.
PAGE 936
SAM D21 Family AC – Analog Comparators To remove the need for polling, an additional means of starting the comparison is also available. A read of the Status C register (STATUSC) will start a comparison on all comparators currently configured for single-shot operation. The read will stall the bus until all enabled comparators are ready. If a comparator is already busy with a comparison, the read will stall until the current comparison is compete, and a new comparison will not be started.
PAGE 937
SAM D21 Family AC – Analog Comparators Window mode is enabled by the Window Enable x bit in the Window Control register (WINCTRL.WENx). Both comparators in a pair must have the same measurement mode setting in their respective Comparator Control Registers (COMPCTRLx.SINGLE). To physically configure the pair of comparators for window mode, the same I/O pin must be chosen as positive input for each comparator, providing a shared input signal. The negative inputs define the range for the window.
PAGE 938
SAM D21 Family AC – Analog Comparators to settle. If the supply voltage is guaranteed to be above 2.5V, the voltage doubler can be disabled by writing the Low-Power Mux bit in the Control A register (CTRLA.LPMUX) to one. Disabling the voltage doubler saves power and reduces the start-up time. 34.6.6 VDDANA Scaler The VDDANA scaler generates a reference voltage that is a fraction of the device’s supply voltage, with 64 levels. One independent voltage channel is dedicated for each comparator.
PAGE 939
SAM D21 Family AC – Analog Comparators comparator. Filtering is selectable from none, 3-bit majority (N=3) or 5-bit majority (N=5) functions. Any change in the comparator output is considered valid only if N/2+1 out of the last N samples agree. The filter sampling rate is the GCLK_AC frequency. Note that filtering creates an additional delay of N-1 sampling cycles from when a comparison is started until the comparator output is validated.
PAGE 940
SAM D21 Family AC – Analog Comparators Figure 34-9. Input Swapping for Offset Compensation + MUXPOS COMPx - CMPx HYSTERESIS ENABLE SWAP MUXNEG COMPCTRLx SWAP 34.6.12 Interrupts The AC has the following interrupt sources: • • Comparator (COMP0, COMP1, COMP2, COMP3): Indicates a change in comparator status. Window (WIN0, WIN1): Indicates a change in the window status.
PAGE 941
SAM D21 Family AC – Analog Comparators Writing a one to an Event Input bit into the Event Control register (EVCTRL.COMPEIx) enables the corresponding action on input event. Writing a zero to this bit disables the corresponding action on input event. Note that if several events are connected to the AC, the enabled action will be taken on any of the incoming events. Refer to the Event System chapter for details on configuring the event system. When EVCTRL.
PAGE 942
SAM D21 Family AC – Analog Comparators then disabled again automatically, unless configured to wake the system from sleep. Filtering is allowed with this configuration. Figure 34-11. Single-Shot SleepWalking GCLK_AC tSTARTUP tSTARTUP Input Event Comparator Output or Event 34.6.15 Synchronization Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read.
PAGE 943
SAM D21 Family AC – Analog Comparators 34.7 Register Summary Offset Name Bit Pos.
PAGE 944
SAM D21 Family AC – Analog Comparators Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. © 2018 Microchip Technology Inc.
PAGE 945
SAM D21 Family AC – Analog Comparators 34.8.1 Control A Name: Offset: Reset: Property: Bit 7 Access Reset CTRLA 0x00 0x00 PAC Write-Protection, Write-Synchronized 2 1 0 LPMUX 6 5 4 3 RUNSTDBY ENABLE SWRST R/W R/W R/W R/W 0 0 0 0 Bit 7 – LPMUX Low-Power Mux This bit is not synchronized Value 0 1 Description The analog input muxes have low resistance, but consume more power at lower voltages (e.g., are driven by the voltage doubler).
PAGE 946
SAM D21 Family AC – Analog Comparators Value 0 1 Description There is no reset operation ongoing. The reset operation is ongoing. © 2018 Microchip Technology Inc.
PAGE 947
SAM D21 Family AC – Analog Comparators 34.8.2 Control B Name: Offset: Reset: Property: Bit 7 CTRLB 0x01 0x00 – 6 5 4 Access Reset 3 2 1 0 STARTx STARTx STARTx STARTx R/W R/W R/W R/W 0 0 0 0 Bits 3,2,1,0 – STARTx Comparator x Start Comparison Writing a '0' to this field has no effect. Writing a '1' to STARTx starts a single-shot comparison on COMPx if both the Single-Shot and Enable bits in the Comparator x Control Register are '1' (COMPCTRLx.SINGLE and COMPCTRLx.ENABLE).
PAGE 948
SAM D21 Family AC – Analog Comparators 34.8.
PAGE 949
SAM D21 Family AC – Analog Comparators 34.8.4 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x04 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
PAGE 950
SAM D21 Family AC – Analog Comparators 34.8.5 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x05 0x00 PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
PAGE 951
SAM D21 Family AC – Analog Comparators 34.8.6 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 INTFLAG 0x06 0x00 – 6 Access Reset 5 4 3 2 1 0 WINx WINx COMPx COMPx COMPx COMPx R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 5,4 – WINx Window x This flag is set according to the Window x Interrupt Selection bit group in the WINCTRL register (WINCTRL.WINTSELx) and will generate an interrupt if INTENCLR/SET.WINx is also one. Writing a '0' to this bit has no effect.
PAGE 952
SAM D21 Family AC – Analog Comparators 34.8.7 Status A Name: Offset: Reset: Property: Bit STATUSA 0x08 0x00 – 7 6 5 WSTATE1[1:0] 4 WSTATE0[1:0] 3 2 1 0 STATEx STATEx STATEx STATEx Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:6 – WSTATE1[1:0] Window 1 Current State These bits show the current state of the signal if the window 1 mode is enabled.
PAGE 953
SAM D21 Family AC – Analog Comparators 34.8.8 Status B Name: Offset: Reset: Property: Bit 7 STATUSB 0x09 0x00 – 3 2 1 0 SYNCBUSY 6 5 4 READYx READYx READYx READYx Access R R R R R Reset 0 0 0 0 0 Bit 7 – SYNCBUSY Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started.
PAGE 954
SAM D21 Family AC – Analog Comparators 34.8.9 Status C Name: Offset: Reset: Property: STATUSC 0x0A 0x00 – STATUSC is a copy of STATUSA (see STATUSA register), with the additional feature of automatically starting single-shot comparisons. A read of STATUSC will start a comparison on all comparators currently configured for single-shot operation. The read will stall the bus until all enabled comparators are ready.
PAGE 955
SAM D21 Family AC – Analog Comparators 34.8.10 Window Control Name: Offset: Reset: Property: Bit 7 WINCTRL 0x0C 0x00 PAC Write-Protection, Write-Synchronized 6 5 4 WINTSEL1[1:0] Access Reset 3 WEN1 2 1 WINTSEL0[1:0] 0 WEN0 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 6:5 – WINTSEL1[1:0] Window 1 Interrupt Selection These bits configure the interrupt mode for the comparator window 1 mode.
PAGE 956
SAM D21 Family AC – Analog Comparators 34.8.11 Comparator Control n Name: Offset: Reset: Property: Bit COMPCTRL 0x10 + n*0x04 [n=0..
PAGE 957
SAM D21 Family AC – Analog Comparators Value 1 Name Hysteresis is enabled. Bits 17:16 – OUT[1:0] Output These bits configure the output selection for comparator n. COMPCTRLn.OUT can be written only while COMPCTRLn.ENABLE is zero. These bits are not synchronized.
PAGE 958
SAM D21 Family AC – Analog Comparators Value 0x5 0x6 0x7 Name VSCALE BANDGAP DAC Description VDD scaler Internal bandgap voltage DAC output Bits 6:5 – INTSEL[1:0] Interrupt Selection These bits select the condition for comparator n to generate an interrupt or event. COMPCTRLn.INTSEL can be written only while COMPCTRLn.ENABLE is zero. These bits are not synchronized.
PAGE 959
SAM D21 Family AC – Analog Comparators 34.8.12 Scaler n Name: Offset: Reset: Property: Bit 7 SCALER 0x20 + n*0x01 [n=0..1] 0x00 PAC Write-Protection 6 5 4 3 2 1 0 VALUE[5:0] Access Reset R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 5:0 – VALUE[5:0] Scaler Value These bits define the scaling factor for channel n of the VDD voltage scaler. The output voltage, VSCALE, is: �SCALE = �DD ⋅ VALUE+1 64 © 2018 Microchip Technology Inc.
PAGE 960
SAM D21 Family DAC – Digital-to-Analog Converter 35. DAC – Digital-to-Analog Converter 35.1 Overview The Digital-to-Analog Converter (DAC) converts a digital value to a voltage. The DAC has one channel with 10-bit resolution, and it is capable of converting up to 350,000 samples per second (350ksps). 35.2 Features • • • • • • 35.
PAGE 961
SAM D21 Family DAC – Digital-to-Analog Converter Related Links 23. PORT - I/O Pin Controller 35.5.2 Power Management The DAC will continue to operate in any Sleep mode where the selected source clock is running. The DAC interrupts can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations in the system without exiting sleep modes. Related Links 16. PM – Power Manager 35.5.
PAGE 962
SAM D21 Family DAC – Digital-to-Analog Converter configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 35.5.
PAGE 963
SAM D21 Family DAC – Digital-to-Analog Converter 35.6.2.3 Enabling the Output Buffer To enable the DAC output on the VOUT pin, the output driver must be enabled by writing a one to the External Output Enable bit in the Control B register (CTRLB.EOEN). The DAC output buffer provides a high-drive-strength output, and is capable of driving both resistive and capacitive loads. To minimize power consumption, the output buffer should be enabled only when external output is needed. 35.6.2.
PAGE 964
SAM D21 Family DAC – Digital-to-Analog Converter (INTENSET), and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the DAC is reset. See INTFLAG register for details on how to clear interrupt flags.
PAGE 965
SAM D21 Family DAC – Digital-to-Analog Converter • • Synchronization when written and read No synchronization When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. If an operation that requires synchronization is executed while its busy bit is one, the operation is discarded and an error is generated.
PAGE 966
SAM D21 Family DAC – Digital-to-Analog Converter 35.7 Register Summary Offset Name Bit Pos. 0x00 CTRLA 7:0 0x01 CTRLB 7:0 0x02 EVCTRL 7:0 RUNSTDBY REFSEL[1:0] BDWP VPD LEFTADJ ENABLE SWRST IOEN EOEN EMPTYEO STARTEI 0x03 Reserved 0x04 INTENCLR 7:0 SYNCRDY EMPTY UNDERRUN 0x05 INTENSET 7:0 SYNCRDY EMPTY UNDERRUN 0x06 INTFLAG 7:0 SYNCRDY EMPTY UNDERRUN 0x07 STATUS 7:0 0x08 DATA SYNCBUSY 7:0 DATA[7:0] 15:8 DATA[15:8] 0x0A ... Reserved 0x0B 0x0C 35.
PAGE 967
SAM D21 Family DAC – Digital-to-Analog Converter 35.8.1 Control A Name: Offset: Reset: Property: Bit 7 CTRLA 0x00 0x00 PAC Write-Protection, Write-Synchronized 6 5 4 3 Access Reset 2 1 0 RUNSTDBY ENABLE SWRST R/W R/W R/W 0 0 0 Bit 2 – RUNSTDBY Run in Standby This bit is not synchronized Value 0 1 Description The DAC output buffer is disabled in standby sleep mode. The DAC output buffer can be enabled in standby sleep mode.
PAGE 968
SAM D21 Family DAC – Digital-to-Analog Converter 35.8.2 Control B Name: Offset: Reset: Property: Bit CTRLB 0x01 0x00 PAC Write-Protection, Enable-Protected 7 6 5 REFSEL[1:0] Access Reset 4 3 2 1 0 BDWP VPD LEFTADJ IOEN EOEN R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Bits 7:6 – REFSEL[1:0] Reference Selection This bit field selects the Reference Voltage for the DAC.
PAGE 969
SAM D21 Family DAC – Digital-to-Analog Converter Value 0 1 Description The DAC output is turned off. The high-drive output buffer drives the DAC output to the internal ADC Positive Mux Input Selection and to the VOUT pin. © 2018 Microchip Technology Inc.
PAGE 970
SAM D21 Family DAC – Digital-to-Analog Converter 35.8.3 Event Control Name: Offset: Reset: Property: Bit 7 EVCTRL 0x02 0x00 PAC Write-Protection 6 5 4 3 2 Access Reset 1 0 EMPTYEO STARTEI R/W R/W 0 0 Bit 1 – EMPTYEO Data Buffer Empty Event Output This bit indicates whether or not the Data Buffer Empty event is enabled and will be generated when the Data Buffer register is empty. Value 0 1 Description Data Buffer Empty event is disabled and will not be generated.
PAGE 971
SAM D21 Family DAC – Digital-to-Analog Converter 35.8.4 Interrupt Enable Clear Name: Offset: Reset: Property: INTENCLR 0x04 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
PAGE 972
SAM D21 Family DAC – Digital-to-Analog Converter 35.8.5 Interrupt Enable Set Name: Offset: Reset: Property: INTENSET 0x05 0x00 PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
PAGE 973
SAM D21 Family DAC – Digital-to-Analog Converter 35.8.6 Interrupt Flag Status and Clear Name: Offset: Reset: Property: Bit 7 INTFLAG 0x06 0x00 PAC Write-Protection 6 5 4 3 Access Reset 2 1 0 SYNCRDY EMPTY UNDERRUN R/W R/W R/W 0 0 0 Bit 2 – SYNCRDY Synchronization Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Synchronization Ready Interrupt Enable bit, which disables the Synchronization Ready interrupt.
PAGE 974
SAM D21 Family DAC – Digital-to-Analog Converter 35.8.7 Status Name: Offset: Reset: Property: Bit 7 STATUS 0x07 0x00 - 6 5 4 3 2 1 0 SYNCBUSY Access R Reset 0 Bit 7 – SYNCBUSY Synchronization Busy Status This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. © 2018 Microchip Technology Inc.
PAGE 975
SAM D21 Family DAC – Digital-to-Analog Converter 35.8.8 Data DAC Name: Offset: Reset: Property: Bit 15 DATA 0x08 0x0000 PAC Write-Protection, Write-Synchronized 14 13 12 11 10 9 8 DATA[15:8] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – DATA[15:0] Data value to be converted DATA register contains the 10-bit value that is converted to a voltage by the DAC.
PAGE 976
SAM D21 Family DAC – Digital-to-Analog Converter 35.8.9 Data Buffer Name: Offset: Reset: Property: Bit 15 DATABUF 0x0C 0x0000 Write-Synchronized 14 13 12 11 10 9 8 DATABUF[15:8] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATABUF[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – DATABUF[15:0] Data Buffer DATABUF contains the value to be transferred into DATA register. © 2018 Microchip Technology Inc.
PAGE 977
SAM D21 Family Peripheral Touch Controller (PTC) 36. Peripheral Touch Controller (PTC) 36.1 Overview The Peripheral Touch Controller (PTC) acquires signals in order to detect a touch on the capacitive sensors. The external capacitive touch sensor is typically formed on a PCB, and the sensor electrodes are connected to the analog front end of the PTC through the I/O pins in the device. The PTC supports both self- and mutual-capacitance sensors.
PAGE 978
SAM D21 Family Peripheral Touch Controller (PTC) 36.3 Block Diagram Figure 36-1. PTC Block Diagram Mutual-Capacitance Input Control Compensation Circuit Y0 RS Y1 Acquisition Module IRQ - Gain control - ADC - Filtering Ym Result 10 CX0Y0 X0 X Line Driver X1 C XnYm Xn Note: For SAM D21 the RS = 0, 20, 50, 100 KΩ. Figure 36-2.
PAGE 979
SAM D21 Family Peripheral Touch Controller (PTC) 36.4 Signal Description Table 36-1. Signal Description for PTC Name Type Description Y[m:0] Analog Y-line (Input/Output) X[n:0] Digital X-line (Output) Note: The number of X- and Y-lines are device dependent. Refer to Configuration Summary for details. Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be mapped on several pins. Related Links 7. I/O Multiplexing and Considerations 2.
PAGE 980
SAM D21 Family Peripheral Touch Controller (PTC) Figure 36-3. Mutual Capacitance Sensor Arrangement Sensor Capacitance Cx,y MCU X0 X1 Cx0,y0 Cx0,y1 Cx0,ym Cx1,y0 Cx1,y1 Cx1,ym Cxn,y0 Cxn,y1 Cxn,ym Xn PTC PTC Module Module Y0 Y1 Ym 36.5.1.2 Self-Capacitance Sensor Arrangement A self-capacitance sensor is connected to a single pin on the Peripheral Touch Controller through the Y electrode for sensing the signal. The sense electrode capacitance is measured by the Peripheral Touch Controller.
PAGE 981
SAM D21 Family Peripheral Touch Controller (PTC) bus clock (CLK_APB). A number of clock sources can be selected as the source for the asynchronous GCLK_PTC. The clock source is selected by configuring the Generic Clock Selection ID in the Generic Clock Control register. For more information about selecting the clock sources, refer to GCLK - Generic Clock Controller. The selected clock must be enabled in the Power Manager, before it can be used by the PTC. By default these clocks are disabled.
PAGE 982
SAM D21 Family Electrical Characteristics 37. Electrical Characteristics 37.1 Disclaimer All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid across operating temperature and voltage unless otherwise specified. 37.2 Thermal Considerations Related Links 37.2.2 Junction Temperature 37.2.1 Thermal Resistance Data The following Table summarizes the thermal resistance data depending on the package. Table 37-1. Thermal Resistance Data 37.2.
PAGE 983
SAM D21 Family Electrical Characteristics Related Links 37.2 Thermal Considerations 37.3 Absolute Maximum Ratings Stresses beyond those listed in this section may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 37-2.
PAGE 984
SAM D21 Family Electrical Characteristics ...........continued Symbol Parameter VDDANA Min. Typ. Max. Units Analog supply voltage 1.62(1) 3.3 3.63 V TA Temperature range -40 25 85 °C TJ Junction temperature - - 100 °C 1. 37.5 Condition With BOD33 disabled. If the BOD33 is enabled, check Table 37-21.
PAGE 985
SAM D21 Family Electrical Characteristics 37.6 Maximum Clock Frequencies Table 37-6. Maximum GCLK Generator Output Frequencies Symbol Description Conditions Max. Units fGCLKGEN0 / fGCLK_MAIN fGCLKGEN1 GCLK Generator Output Frequency Undivided 96 MHz Divided 48 MHz fGCLKGEN2 fGCLKGEN3 fGCLKGEN4 fGCLKGEN5 fGCLKGEN6 fGCLKGEN7 fGCLKGEN8 Table 37-7. Maximum Peripheral Clock Frequencies Symbol Description Max.
PAGE 986
SAM D21 Family Electrical Characteristics ...........continued 37.7 Symbol Description Max.
PAGE 987
SAM D21 Family Electrical Characteristics • • • • • • • • • – VDDIN = 1.8V, CPU is running on Flash with three wait states Wake up time from sleep mode is measured from the edge of the wakeup signal to the execution of the first instruction fetched in flash.
PAGE 988
SAM D21 Family Electrical Characteristics Table 37-8. Current Consumption (Device Variant A) Mode Conditions TA Min. Typ. Max. Units ACTIVE CPU running a While(1) algorithm 25°C 3.11 3.37 3.64 mA 85°C 3.24 3.48 3.76 CPU running a While(1) algorithm VDDIN=1.8V, CPU is running on Flash with 3 wait states 25°C 3.10 3.36 3.64 85°C 3.24 3.48 3.
PAGE 989
SAM D21 Family Electrical Characteristics ...........continued Mode Conditions TA Min. Typ. Max. Units IDLE0 Default operating conditions 25°C 1.89 2.04 2.20 mA 85°C 1.98 2.14 2.33 25°C 1.34 1.46 1.58 85°C 1.41 1.55 1.71 25°C 1.07 1.17 1.28 85°C 1.13 1.27 1.40 25°C - 4.06 12.8 85°C - 55.2 100 25°C - 2.70 12.2 85°C - 53.
PAGE 990
SAM D21 Family Electrical Characteristics ...........continued Mode Conditions IDLE0 Default operating conditions IDLE1 IDLE2 Default operating conditions Default operating conditions STANDBY XOSC32K running, RTC running at 1kHz XOSC32K and RTC stopped © 2018 Microchip Technology Inc. TA VCC Typ. Max. 25°C 3.3V 2.4 2.5 85°C 3.3V 2.5 2.6 25°C 3.3V 1.8 1.9 85°C 3.3V 1.9 2.0 25°C 3.3V 1.3 1.4 85°C 3.3V 1.4 1.5 25°C 3.3V 4 6.2 85°C 3.3V 54 100 25°C 3.3V 2.8 5.0 85°C 3.
PAGE 991
SAM D21 Family Electrical Characteristics Table 37-10. Current Consumption (Device Variant B, C, D, L with Silicon Revision F and Silicon Revision G) Mode Conditions ACTIVE IDLE0 IDLE1 IDLE2 VCC Typ. Max. CPU running a While 1 algorithm 25°C 3.3V 3.7 3.9 85°C 3.3V 3.8 4 CPU running a While 1 algorithm 25°C 1.8V 3.7 3.9 85°C 1,8V 3.8 4 CPU running a While 1 algorithm, with GCLKIN as reference 25°C 3.3V 72*Freq+107 76*Freq+111 85°C 3.
PAGE 992
SAM D21 Family Electrical Characteristics Table 37-11. Wake-up Time Mode Conditions TA IDLE0 OSC8M used as main clock source, Cache disabled 25°C - 4.0 - 85°C - 4.0 - 25°C - 12.1 - 85°C - 13.6 - 25°C - 13.0 - 85°C - 14.5 - 25°C - 19.6 - 85°C - 19.7 - IDLE1 IDLE2 STANDBY IOSC8M used as main clock source, Cache disabled IOSC8M used as main clock source, Cache disabled IOSC8M used as main clock source, Cache disabled Min. Typ. Max. Units μs Figure 37-1.
PAGE 993
SAM D21 Family Electrical Characteristics • • • • • • • – XOSC (crystal oscillator) stopped – XOSC32K (32 kHz crystal oscillator) running with external 32kHz crystal – OSC8M at 8MHz Clocks – OSC8M used as main clock source – CPU, AHB and APBn clocks undivided The following AHB module clocks are running: NVMCTRL, HPB2 bridge, HPB1 bridge, HPB0 bridge – All other AHB clocks stopped The following peripheral clocks running: PM, SYSCTRL – All other peripheral clocks stopped I/Os are inactive with internal pu
PAGE 994
SAM D21 Family Electrical Characteristics ...........continued Peripheral Conditions Typ. Units SERCOMx.USART fGCLK=8MHz, Enable 65.5 μA I2S(3) fGCLK_I2S_0=12.288MHz with source FDPLL with fFDPLL=49,152MHz 26.4 μA DMAC(4) RAM to RAM transfer 399.5 μA Note: 1. All TCs from 4 to 7 share the same power consumption values. 2. All SERCOMs from 0 to 5 share the same power consumption values. 3. The value includes the power consumption of the FDPLL. 4.
PAGE 995
SAM D21 Family Electrical Characteristics Table 37-13. Typical USB Device Full Speed mode Current Consumption USB Device state Conditions Typ. Units Suspend GCLK_USB is off, using USB wakeup asynchronous interrupt. USB bus in suspend mode. 201 Suspend GCLK_USB is on. USB bus in suspend mode. 0.83 mA IDLE Start Of Frame is running. No packet transferred. 1.17 mA Active OUT Start Of Frame is running. Bulk OUT on 100% bandwidth. 2.17 mA Active IN Start Of Frame is running.
PAGE 996
SAM D21 Family Electrical Characteristics ...........continued Symbol Parameter Conditions Min. Typ. Max. VIL Input low-level voltage VDD=1.62V-2.7V - - 0.25*VDD V VDD=2.7V-3.63V - - 0.3*VDD Input high-level voltage VDD=1.62V-2.7V 0.7*VDD - - VDD=2.7V-3.63V 0.55*VDD - - VOL Output low-level voltage VDD>1.6V, IOL maxI - 0.1*VDD 0.2*VDD VOH Output high-level VDD>1.6V, IOH maxII voltage 0.8*VDD 0.9*VDD - IOL Output low-level current VDD=1.62V-3V, PORT.PINCFG.
PAGE 997
SAM D21 Family Electrical Characteristics 37.9.2 I2C Pins Refer to I/O Multiplexing and Considerations to get the list of I2C pins. Table 37-16. I2C Pins Characteristics in I2C configuration Symbol Parameter Condition Min. Typ. Max. VIL VDD=1.62V-2.7V - - 0.25*VDD V VDD=2.7V-3.63V - - 0.3*VDD VDD=1.62V-2.7V 0.7*VDD - - VDD=2.7V-3.63V 0.55*VDD - - 0.08*VDD - - VDD> 2.0V, IOL=3mA - - 0.4 VDD≤2.0V , IOL=2mA - - 0.2*VDD VOL =0.4V Standard, Fast and HS Modes 3 VOL =0.
PAGE 998
SAM D21 Family Electrical Characteristics Table 37-17. Injection Current(1) Symbol Description min max Unit Iinj1 (2) IO pin injection current -1 +1 mA Iinj2 (3) IO pin injection current -15 +15 mA Iinjtotal Sum of IO pins injection current -45 +45 mA 1. 2. Injecting current may have an effect on the accuracy of Analog blocks Conditions for Vpin: Vpin < GND-0.6V or 3.6V
PAGE 999
SAM D21 Family Electrical Characteristics Note: 2. It is recommended to use ceramic or solid tantalum capacitor with low ESR <= 1 ohms. 37.11.2 Power-On Reset (POR) Characteristics Table 37-20. POR Characteristics Symbol Parameter Conditions Min. Typ. Max. Units VPOT+ Voltage threshold on VDD rising VDD falls at 1V/ms or slower 1.27 1.45 1.58 V VPOT- Voltage threshold on VDD falling 0.72 0.99 1.32 V VDD Figure 37-2. POR Operating Principle VPOT+ VPOT- Reset Time 37.11.
PAGE 1000
SAM D21 Family Electrical Characteristics Table 37-21. BOD33 LEVEL Value (Silicon Revisions A, B, C, D, E, and F) Symbol BOD33.LEVEL VBOD+ Conditions Min. Typ. Max. - 1.715 1.745 7 - 1.750 1.779 39 - 2.84 2.92 48 - 3.2 3.3 1.62 1.64 1.67 1.64 1.675 1.71 2.72 2.77 2.81 3.0 3.07 3.2 6 VBODor Hysteresis ON 6 Hysteresis ON or 7 VBOD Hysteresis OFF 39 48 Units V Note: See chapter Memories table NVM User Row Mapping for the BOD33 default value settings. Table 37-22.
PAGE 1001
SAM D21 Family Electrical Characteristics ...........continued Symbol tSTARTUP Parameter Conditions Min. Typ. - - 2.2(1) Startup time Max. Units - μs Note: 1. These values are based on simulation. These values are not covered by test limits in production or characterization. Related Links 10.3.1 NVM User Row Mapping 37.11.4 Analog-to-Digital (ADC) characteristics Table 37-24. Operating Conditions Symbol Parameter RES fCLK_ADC Min. Typ. Max.
PAGE 1002
SAM D21 Family Electrical Characteristics ...........continued Symbol Parameter Conditions Min. Typ. Max. Units IDD DC supply current(1) fCLK_ADC = 2.1MHz(3) - 1.25 1.79 mA Note: 1. These values are based on characterization. These values are not covered by test limits in production. 2. These values are based on simulation. These values are not covered by test limits in production or characterization. 3.
PAGE 1003
SAM D21 Family Electrical Characteristics ...........continued Symbol Parameter Conditions Min. Typ. Max. Units INLI Integral Non Linearity 1x gain 0.9 1.3 4.0 LSB DNL Differential Non Linearity 1x gain +/-0.3 +/-0.5 +/-0.95 LSB Gain Error Ext. Ref 1x -10.0 1.3 +10.0 mV VREF=VDDANA/1.48 -20.0 -10.0 +10.0 mV Bandgap -20.0 -2.0 +20.0 mV Ext. Ref. 0.5x +/-0.02 +/-0.05 +/-0.1 % Ext. Ref. 2x to 16x +/-0.01 +/-0.03 +/-0.5 % Ext. Ref. 1x -5.0 -1.0 +5.
PAGE 1004
SAM D21 Family Electrical Characteristics ...........continued Symbol Parameter Conditions Min. Typ. Max. Units TUE Total Unadjusted Error 1x gain - 10.5 14.0 LSB INL Integral Non-Linearity 1x gain 1.0 1.6 3.5 LSB DNL Differential Non-Linearity 1x gain +/-0.5 +/-0.6 +/-0.95 LSB Gain Error Ext. Ref. 1x -5.0 0.7 +5.0 Gain Accuracy(4) Ext. Ref. 0.5x +/-0.2 +/-0.34 +/-0.4 Ext. Ref. 2x to 16X +/-0.01 +/-0.1 +/-0.2 % Offset Error Ext. Ref. 1x -5.0 1.5 +5.
PAGE 1005
SAM D21 Family Electrical Characteristics 3. 4. – VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V – VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (Vref/GAIN) 37.11.4.
PAGE 1006
SAM D21 Family Electrical Characteristics Table 37-31. Offset and Gain correction feature Gain Factor Conditions Offset Error (mV) 0.5x 1x In differential mode, 1x gain, VDDANA=3.0V, 0.25 VREF=1.0V, 350kSps at 25°C 0.20 2x Gain Error Total Unadjusted (mV) Error (LSB) 1.0 2.4 0.10 1.5 0.15 -0.15 2.7 8x -0.05 0.05 3.2 16x 0.10 -0.05 6.1 37.11.4.
PAGE 1007
SAM D21 Family Electrical Characteristics 37.11.5 Digital to Analog Converter (DAC) Characteristics Table 37-32. Operating Conditions(1) Symbol Parameter Conditions Min. Typ. Max. Units VDDANA Analog supply voltage 1.62 - 3.63 V AVREF External reference voltage 1.0 - VDDANA-0.6 V Internal reference voltage 1 - 1 - V Internal reference voltage 2 - VDDANA - V Linear output voltage range 0.05 - VDDANA-0.
PAGE 1008
SAM D21 Family Electrical Characteristics ...........continued Symbol Parameter Conditions DNL Differential non-linearity VREF= Ext 1.0V VREF= VDDANA VREF= INT1V Min. Typ. Max. Units VDD = 1.6V +/-0.9 +/-1.2 +/-1.5 LSB VDD = 3.6V +/-0.9 +/-1.1 +/-1.2 VDD = 1.6V +/-1.1 +/-1.5 +/-1.7 VDD = 3.6V +/-1.0 +/-1.1 +/-1.2 VDD = 1.6V +/-1.1 +/-1.4 +/-1.5 VDD = 3.6V +/-1.0 +/-1.5 +/-1.6 Gain error Ext. VREF +/-1.5 +/-5 +/-10 mV Offset error Ext.
PAGE 1009
SAM D21 Family Electrical Characteristics 37.11.6 Analog Comparator Characteristics Table 37-36. Electrical and Timing (Device Variant A) Symbol Parameter Min. Typ. Max. Positive input voltage range 0 - VDDANA V Negative input voltage range 0 - VDDANA Hysteresis = 0, Fast mode -15 0.0 +15 mV Hysteresis = 0, Low power mode -25 0.
PAGE 1010
SAM D21 Family Electrical Characteristics ...........continued Symbol Parameter Conditions Min. Typ. Max. Units Changes for VACM=VDDANA/2 100mV overdrive, Fast mode - 90 180 ns Changes for VACM=VDDANA/2 100mV overdrive, Low power mode 282 520 ns Enable to ready delay Fast mode - 1 2.6 μs Enable to ready delay Low power mode - 14 22 μs INL(3) -1.4 0.75 +1.4 LSB DNL(3) -0.9 0.25 +0.9 LSB Offset Error (1)(2) -0.200 0.260 +0.920 LSB Gain Error (1)(2) -0.
PAGE 1011
SAM D21 Family Electrical Characteristics ...........continued Symbol Parameter Temperature Sensor accuracy Conditions Min. Typ. Max. Units Using the method described in the 37.11.8.2 Software-based Refinement of the Actual Temperature -10 10 - °C Table 37-40. Temperature Sensor Characteristics(1) (Device Variant B,C, D and L) Symbol Parameter Temperature sensor output voltage Conditions Min. Typ. T= 25°C, VDDANA = 3.3V - Max. Units 0.688 - V Temperature sensor slope 2.06 2.16 2.
PAGE 1012
SAM D21 Family Electrical Characteristics ...........continued Bit position Name Description 23:20 HOT_TEMP_VAL_DEC Decimal part of hot temperature 31:24 ROOM_INT1V_VAL 2’s complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) 39:32 HOT_INT1V_VAL 2’s complement of the internal 1V reference drift at hot temperature (versus a 1.
PAGE 1013
SAM D21 Family Electrical Characteristics �ADC + − �ADCR �ADCH + − �ADCR = temp+ − temp� temp� + − temp� Given a temperature sensor ADC conversion value ADCm, we can infer a coarse value of the temperature tempC as: temp� = temp� + ADC� ⋅ [Equation 1] 1 212 + − 1 ADC� ⋅ + − ADC� ⋅ INT1�� 12 2 + −1 INT1�� 12 2 + −1 + − ADC� ⋅ ⋅ temp� + − temp� INT1�� 12 2 + −1 Note: 1. In the previous expression, we have added the conversion of the ADC register value to be expressed in V. 2.
PAGE 1014
SAM D21 Family Electrical Characteristics 37.12 NVM Characteristics Table 37-42. Maximum Operating Frequency VDD range NVM Wait States Maximum Operating Frequency Units 1.62V to 2.7V 0 14 MHz 1 28 2 42 3 48 0 24 1 48 2.7V to 3.63V Note that on this flash technology, a max number of 8 consecutive write is allowed per row. Once this number is reached, a row erase is mandatory. Table 37-43. Flash Endurance and Data Retention Symbol Parameter Conditions Min. Typ. Max.
PAGE 1015
SAM D21 Family Electrical Characteristics Table 37-46. NVM Characteristics (Device Variant B,C, D and L) 37.13 Symbol Parameter Conditions Min. Typ. Max. Units tFPP Page programming time - - - 2.5 ms tFRE Row erase time - - 1.2 6 ms tFCE DSU chip erase time (CHIP_ERASE) - - - 240 ms Oscillators Characteristics 37.13.1 Crystal Oscillator (XOSC) Characteristics 37.13.1.
PAGE 1016
SAM D21 Family Electrical Characteristics ...........continued Symbol Parameter CXOUT Conditions Min. Typ. Max. Units - 3.
PAGE 1017
SAM D21 Family Electrical Characteristics 37.13.2 External 32 kHz Crystal Oscillator (XOSC32K) Characteristics 37.13.2.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin. Table 37-49. Digital Clock Characteristics Symbol Parameter fCPXIN32 Conditions Min. Typ. Max. Units XIN32 clock frequency - 32.768 - kHz XIN32 clock duty cycle - 50 - % 37.13.2.1.
PAGE 1018
SAM D21 Family Electrical Characteristics ...........continued Symbol Parameter Conditions Min. Typ. Max. Units ESR CL=12.5pF - 100 Crystal equivalent series resistance f=32.768kHz , Safety Factor = 3 - kΩ 37.13.3 Digital Frequency Locked Loop (DFLL48M) Characteristics Table 37-52. DFLL48M Characteristics - Open Loop Mode(1) Symbol Parameter Conditions Min. Typ. Max. Units fOUT Output frequency DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.
PAGE 1019
SAM D21 Family Electrical Characteristics ...........continued Symbol Parameter Conditions Min. Typ. Max. Units tLOCK fREF = XTAL, 32 .768kHz, 100ppm DFLLMUL = 1464 DFLLVAL.COARSE = DFLL48M COARSE CAL 100 200 500 μs Lock time DFLLVAL.FINE = 512 DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10 Table 37-54. DFLL48M Characteristics - Closed Loop Mode(1) (Device Variant B, C, D, and L) Symbol Parameter Conditions Min. Typ. Max.
PAGE 1020
SAM D21 Family Electrical Characteristics 37.13.4 32.768kHz Internal oscillator (OSC32K) Characteristics Table 37-55. 32kHz RC Oscillator Characteristics Symbol Parameter Conditions Min. fOUT Calibrated against a 32.768kHz reference at 25°C, over [-40, +85]C, over [1.62, 3.63]V 28.508 32.768 34.734 kHz Calibrated against a 32.768kHz reference at 25°C, at VDD=3.3V 32.276 32.768 33.260 Calibrated against a 32.768kHz reference at 25°C, over [1.62, 3.63]V 31.457 32.768 34.
PAGE 1021
SAM D21 Family Electrical Characteristics 37.13.6 8MHz RC Oscillator (OSC8M) Characteristics Table 37-57. Internal 8MHz RC Oscillator Characteristics Symbol Parameter Conditions fOUT Output frequency Calibrated against a 8MHz reference at 7.8 25°C, over [-40, +85]C, over [1.62, 3.63]V TempCo Min. Typ. Max. Units 8 8.16 MHz Calibrated against a 8MHz reference at 7.94 8 25°C, at VDD=3.3V 8.06 Calibrated against a 8MHz reference at 7.92 8 25°C, over [1.62, 3.63]V 8.08 Frequency vs.
PAGE 1022
SAM D21 Family Electrical Characteristics Table 37-59. FDPLL96M Characteristics(1) (Device Variant B and L with Silicon Revision E) Symbol Parameter fIN Input frequency 32 - 2000 KHz fOUT Output frequency 48 - 96 MHz IFDPLL96M Current consumption fIN= 32 kHz, fOUT= 48 MHz - 500 700 μA fIN= 32 kHz, fOUT= 96 MHz - 900 1200 fIN= 32 kHz, fOUT= 48 MHz - 1.5 2.1 fIN= 32 kHz, fOUT= 96 MHz - 4.0 10.0 fIN= 2 MHz, fOUT= 48 MHz - 1.6 2.2 fIN= 2 MHz, fOUT= 96 MHz - 4.6 10.
PAGE 1023
SAM D21 Family Electrical Characteristics 37.14 PTC Typical Characteristics 37.14.1 Device Variant A Figure 37-7. Power Consumption [μA] 1 sensor, noise countermeasures disabled, f=48MHz, Vcc=3.3V 140 120 100 80 Scan rate 10ms 60 Scan rate 50ms 40 Scan rate 100ms Scan rate 200ms 20 0 1 2 4 8 16 32 64 Sample averaging Figure 37-8. Power Consumption [μA] 1 sensor, noise countermeasures Enabled, f=48MHz, Vcc=3.
PAGE 1024
SAM D21 Family Electrical Characteristics Figure 37-9. Power Consumption [μA] 10 sensors, noise countermeasures disabled, f=48MHz, Vcc=3.3V 1200 1000 800 Scan rate 10ms 600 Scan rate 50ms Scan rate 100ms 400 Scan rate 200ms 200 Linear (Scan rate 50ms) 0 1 2 4 8 16 32 64 Sample averaging Figure 37-10. Power Consumption [μA] 10 sensors, noise countermeasures Enabled, f=48MHz, Vcc=3.
PAGE 1025
SAM D21 Family Electrical Characteristics Figure 37-11. Power Consumption [μA] 100 sensors, noise countermeasures disabled, f=48MHz, Vcc=3.3V 5000 4500 4000 3500 3000 Scan rate 10ms 2500 2000 Scan rate 50ms 1500 Scan rate 100ms 1000 Scan rate 200ms 500 0 1 2 4 8 16 32 64 Sample averaging Figure 37-12. Power Consumption [μA] 100 sensors, noise countermeasures Enabled, f=48MHz, Vcc=3.
PAGE 1026
SAM D21 Family Electrical Characteristics Figure 37-13. CPU Utilization 80 % 70 % 60 % 50 % Channel count 1 40 % Channel count 10 30 % Channel count 100 20 % 10 % 0% 10 50 100 200 37.14.2 Device Variant B,C and D VCC = 3.3C and fCPU = 48 MHz for the following PTC measurements. = 4MHz / FREQ_MODE_NONE Figure 37-14. 1 Sensor / PTC_GCLK1Key = 4/ PTC_GCLK MHz / FREQ_MODE_NONE 1 2 4 8 16 32 64 Sample Averaging © 2018 Microchip Technology Inc.
PAGE 1027
SAM D21 Family Electrical Characteristics = 2MHz / FREQ_MODE_HOP Figure 37-15. 1 Sensor / PTC_GCLK1Key = 2/ PTC_GCLK MHz / FREQ_MODE_HOP 1 2 4 8 16 32 64 Sample Averaging 10Keys = 4MHz / FREQ_MODE_NONE Figure 37-16. 10 Sensor / PTC_GCLK = 4/ PTC_GCLK MHz / FREQ_MODE_NONE 1 2 4 8 16 32 64 Sample Averaging © 2018 Microchip Technology Inc.
PAGE 1028
SAM D21 Family Electrical Characteristics 10Keys = 2MHz / FREQ_MODE_HOP Figure 37-17. 10 Sensor / PTC_GCLK = 2/ PTC_GCLK MHz / FREQ_MODE_HOP 1 2 4 8 16 32 64 Sample Averaging 100 Keys = 4MHz / FREQ_MODE_NONE Figure 37-18. 100 Sensor / PTC_GCLK = 4/ PTC_GCLK MHz / FREQ_MODE_NONE 1 2 4 8 16 32 64 Sample Averaging © 2018 Microchip Technology Inc.
PAGE 1029
SAM D21 Family Electrical Characteristics Figure 37-19. 100 Sensor / PTC_GCLK = 2/ PTC_GCLK MHz / FREQ_MODE_HOP 100 Keys = 2MHz / FREQ_MODE_HOP 1 2 4 8 16 32 64 Sample Averaging Table 37-61. Sensor Load Capacitance Symbol Mode PTC channel Max Sensor Load (1) Y0 16 Y1 23 Y2 19 Units Y3 Y4 Y5 Y6 Cload Self-capacitance 23 Y7 Y8 pF Y9 Y10 19 Y11 Y12 Y13 23 Y14 Y15 Mutual-capacitance All 30 Note: 1. Capacitance load that the PTC circuitry can compensate for each channel.
PAGE 1030
SAM D21 Family Electrical Characteristics Table 37-62. Analog Gain Settings Symbol Gain Setting Average GAIN_1 1.0 GAIN_2 2.0 GAIN_4 3.8 GAIN_8 8.0 GAIN_16 12.4 GAIN_32 - Note: 1. Analog Gain is a parameter of the QTouch Library. Refer to the QTouch Library Peripheral Touch Controller User Guide. 2. GAIN_16 and GAIN_32 settings are not recommended, otherwise the PTC measurements might get unstable.
PAGE 1031
SAM D21 Family Electrical Characteristics Table 37-63. Symbol Parameters Drift Calibration PTC scan rate Oversamples (msec) 10 50 Disabled 100 200 IDD Current Consumption 10 50 Enabled 100 200 37.15 Ta Typ.
PAGE 1032
SAM D21 Family Electrical Characteristics Table 37-64. GCLK_USB Clock Setup Recommendations Clock setup DFLL48M FDPLL96M USB Device USB Host Open loop No No Closed loop, any internal OSC source No No Closed loop, any external XOSC source Yes No Closed loop, USB SOF source (USB recovery mode)(1) Yes(2) N/A Any internal OSC source (32K, 8M, ... ) No No Any external XOSC source (< 1MHz) Yes No Any external XOSC source (> 1MHz) Yes(3) Yes Notes: 1.
PAGE 1033
SAM D21 Family Electrical Characteristics 37.16.2 SERCOM in SPI Mode Timing Figure 37-20. SPI Timing Requirements in Master Mode SS tSCKR tMOS tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOH tMOH MOSI (Data Output) MSB LSB Figure 37-21. SPI Timing Requirements in Slave Mode SS tSSS tSCKR tSCKF tSSH SCK (CPOL = 0) tSSCKW SCK (CPOL = 1) tSSCKW tSIS MOSI (Data Input) tSIH MSB tSOSSS MISO (Data Output) © 2018 Microchip Technology Inc.
PAGE 1034
SAM D21 Family Electrical Characteristics Table 37-67. SPI Timing Characteristics and Requirements(1) Symbo Parameter l Conditions tSCK SCK period Master tSCKW SCK high/low width Master - 0.
PAGE 1035
SAM D21 Family Electrical Characteristics Figure 37-22. I2C Interface Bus Timing tOF tHIGH tLOW tR tLOW SCL tSU;STA tHD;STA tHD;DAT tSU;DAT tSU;STO SDA tBUF Table 37-68. I2C Interface Timing (Device Variant A) Symbol Parameter tR tOF Rise time for both SDA and SCL Output fall time from VIHmin to VILmax Conditions Min. Typ. Max.
PAGE 1036
SAM D21 Family Electrical Characteristics Table 37-69. I2C Interface Timing (Device Variant B,C and D) Symbol Parameter tR tOF Rise time for both SDA and SCL Output fall time from VIHmin to VILmax Conditions Min. Typ. Max.
PAGE 1037
SAM D21 Family Electrical Characteristics 37.16.4 SWD Timing Figure 37-23. SWD Interface Signals Read Cycle From debugger to SWDIO pin Stop Park Tri State Thigh Tos Data Data Parity Start Tlow From debugger to SWDCLK pin SWDIO pin to debugger Tri State Acknowledge Tri State Write Cycle From debugger to SWDIO pin Stop Park Tri State Tis Start Tih From debugger to SWDCLK pin SWDIO pin to debugger Tri State Acknowledge Data Data Parity Tri State Table 37-70.
PAGE 1038
SAM D21 Family Electrical Characteristics 37.16.5 I2S Timing Figure 37-24. I2S Timing Master Mode Master mode: SCK, FS and MCK are output MCK output tM_SCKOR SCK output FS output tM_SCKOF tM_FSOH tM_SDIS tM_SCKO tM_SDOH tM_SDIH tM_FSOV tM_SDOV SD output LSB right ch. MSB left ch. SD input Figure 37-25. I2S Timing Slave Mode Slave mode: SCK and FS are input tS_FSIH SCK input tS_SCKI tS_FSIS FS input tS_SDIS tS_SDOH tS_SDIH tS_SDOV SD output LSB rignt ch. MSB left ch.
PAGE 1039
SAM D21 Family Electrical Characteristics ...........continued Name Description Mode VDD=1.8V VDD=3.3V Units Min. Typ. Max Min. Typ. Max.
PAGE 1040
SAM D21 Family Electrical Characteristics ...........continued Name Description Mode VDD=1.8V VDD=3.3V Units Min. Typ. Max Min. Typ. Max. tPDM2LS Data input setup time Master mode PDM2 Left 34.7 24.5 ns tPDM2LH Data input hold time Master mode PDM2 Left -8.2 -8.2 ns tPDM2RS Data input setup time Master mode PDM2 Right 30.5 20.9 ns tPDM2RH Data input hold time Master mode PDM2 Right -6.7 -6.7 ns Table 37-72.
PAGE 1041
SAM D21 Family Electrical Characteristics ...........continued Name Description Mode VDD=1.8V VDD=3.3V Units Min. Typ. Max. Min. Typ. Max. tM_FSOH FS hold time Master mode -0.1 -0.1 ns tS_FSIS FS setup time Slave mode 6 5.3 ns tS_FSIH FS hold time Slave mode 0 0 ns tM_SDIS Data input setup time Master mode 36 25.9 ns tM_SDIH Data input hold time -8.2 -8.2 ns tS_SDIS Data input setup time Slave mode 9.1 8.3 ns tS_SDIH Data input hold time 3.8 3.
PAGE 1042
SAM D21 Family Electrical Characteristics at 105°C 38. Electrical Characteristics at 105°C 38.1 Disclaimer All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid across operating temperature and voltage unless otherwise specified. 38.2 Absolute Maximum Ratings Stresses beyond those listed in table below may cause permanent damage to the device.
PAGE 1043
SAM D21 Family Electrical Characteristics at 105°C 38.6.2.1 BOD33 Characteristics 38.4 Maximum Clock Frequencies Table 38-3. Maximum GCLK Generator Output Frequencies Symbol Description Conditions Max. Units fGCLKGEN0 / fGCLK_MAIN GCLK Generator Output Frequency Undivided 96 MHz Divided 48 MHz fGCLKGEN1 fGCLKGEN2 fGCLKGEN3 fGCLKGEN4 fGCLKGEN5 Table 38-4. Maximum Peripheral Clock Frequencies Symbol Description Max.
PAGE 1044
SAM D21 Family Electrical Characteristics at 105°C ...........continued 38.5 Symbol Description Max.
PAGE 1045
SAM D21 Family Electrical Characteristics at 105°C • • • • • • • – XOSC32K (32 kHz crystal oscillator) stopped – XOSC (crystal oscillator) running with external 32MHz clock on XIN – DFLL48M stopped Clocks – XOSC used as main clock source, except otherwise specified – CPU, AHB clocks undivided – APBA clock divided by 4 – APBB and APBC bridges off The following AHB module clocks are running: NVMCTRL, APBA bridge – All other AHB clocks stopped The following peripheral clocks running: PM, SYSCTRL, RTC – All
PAGE 1046
SAM D21 Family Electrical Characteristics at 105°C Table 38-5. Current Consumption (Silicon Revisions A, B, C, D, E, and F) Mode Conditions TA Max. Units ACTIVE CPU running a While(1) algorithm 105°C - 2.55 2.75 mA CPU running a While(1) algorithm VDDIN=1.8V, CPU is running on Flash with 3 wait states - 2.56 2.
PAGE 1047
SAM D21 Family Electrical Characteristics at 105°C Note: 1. Measurements were done with SYSCTRL->VREG.bit.RUNSTDBY = 1 Table 38-6. Current Consumption (Silicon Revision G) Mode conditions Ta ACTIVE CPU running a While 1 algorithm Max. Units 105°C 3.3V 3.3 3.6 mA 105°C 1.8V 3.3 3.6 CPU running a While 1 algorithm, with GCLKIN as reference 105°C 3.3V 56*Freq +254 55*Freq +596 CPU running a Fibonacci algorithm 105°C 3.3V 4.2 4.6 105°C 1.8V 4.3 4.
PAGE 1048
SAM D21 Family Electrical Characteristics at 105°C Figure 38-1. Measurement Schematic VDDIN VDDANA VDDIO Amp 0 VDDCORE 38.6 Analog Characteristics 38.6.1 Power-On Reset (POR) Characteristics Table 38-8. POR Characteristics Symbol Parameter Conditions Min. Typ. Max. Units VPOT+ Voltage threshold on VDD rising IVDD falls at 1V/ms or slower 1.27 1.45 1.58 V VPOT- Voltage threshold on VDD falling 0.72 0.99 1.32 V © 2018 Microchip Technology Inc.
PAGE 1049
SAM D21 Family Electrical Characteristics at 105°C VDD Figure 38-2. POR Operating Principle VPOT+ VPOT- Reset Time 38.6.2 Brown-Out Detectors Characteristics 38.6.2.1 BOD33 Characteristics Table 38-9. BOD33 Characteristics Symbol Parameter I Step size, between adjacent values in BOD33.LEVEL VHYST VBOD+ - VBOD- tDET Detection time IIdleBOD33 Current consumption om Active/Idle mode Conditions Min. Typ. Max.
PAGE 1050
SAM D21 Family Electrical Characteristics at 105°C ...........continued Symbol Parameter ISbyBOD33 Current consumption in Standby mode Conditions Temp. Sampling mode 25°C 38.6.3 Max. Units 0.132 0.38 μA -40- to 105°C tSTARTUP Startup time 1. Min. Typ. -40- to 105°C 1.5 2.2(1) - - μs These values are based on simulation. These values are not covered by test limits in production or characterization. Analog-to-Digital Converter (ADC) Characteristics Table 38-10.
PAGE 1051
SAM D21 Family Electrical Characteristics at 105°C ...........continued Symbol Parameter RSAMPLE Input channel source resistance(2) IDD DC supply current(1) 1. 2. 3. Conditions fCLK_ADC = 2.1MHz(3) Min. Typ. Max. Units - - 3.5 kΩ - 1.25 1.83 mA These values are based on characterization. These values are not covered by test limits in production. These values are based on simulation. These values are not covered by test limits in production or characterization.
PAGE 1052
SAM D21 Family Electrical Characteristics at 105°C 3.1. 4. 5. If |VIN| > VREF/4 • VCM_IN < 0.95*VDDANA + VREF/4 – 0.75V • VCM_IN > VREF/4 -0.05*VDDANA -0.1V 3.2. If |VIN| < VREF/4 • VCM_IN < 1.2*VDDANA - 0.75V • VCM_IN > 0.2*VDDANA - 0.1V The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply.
PAGE 1053
SAM D21 Family Electrical Characteristics at 105°C 38.6.3.1 Performance with the Averaging Digital Feature Averaging is a feature which increases the sample accuracy. ADC automatically computes an average value of multiple consecutive conversions. The numbers of samples to be averaged is specified by the Number-of-Samples-to-be-collected bit group in the Average Control register (AVGCTRL.SAMPLENUM[3:0]) and the averaged output is available in the Result register (RESULT). Table 38-13.
PAGE 1054
SAM D21 Family Electrical Characteristics at 105°C Figure 38-3. ADC Input VDDANA/2 Analog Input AINx RSOURCE CSAMPLE RSAMPLE VIN To achieve n bits of accuracy, the �SAMPLE capacitor must be charged at least to a voltage of �CSAMPLE ≥ �IN × 1 − 2− �+1 The minimum sampling time �SAMPLEHOLD for a given �SOURCEcan be found using this formula: �SAMPLEHOLD ≥ �SAMPLE + �SOURCE × �SAMPLE × � + 1 × ln 2 for a 12 bits accuracy: �SAMPLEHOLD ≥ �SAMPLE + �SOURCE × �SAMPLE × 9.02 where 38.6.
PAGE 1055
SAM D21 Family Electrical Characteristics at 105°C Table 38-16. Clock and Timing Symbol I Parameter Conditions Conversion rate Cload=100pF Rload > 5kΩ Startup time 1. Min. Typ. Max. Units Normal mode - - 350 ksps For ΔDATA=+/-1 - - 1000 VDDNA > 2.6V - - 2.85 μs VDDNA < 2.6V - - 10 μs These values are based on simulation. These values are not covered by test limits in production or characterization. Table 38-17.
PAGE 1056
SAM D21 Family Electrical Characteristics at 105°C ...........continued Symbol Parameter Conditions Min. Typ. Max. Units Hysteresis = 0, Fast mode -15 0.0 +15 mV Hysteresis = 0, Low power mode -25 0.0 +25 mV Hysteresis = 1, Fast mode 20 50 85 mV Hysteresis = 1, Low power mode 15 40 75 mV Changes for VACM=VDDANA/2 100mV overdrive, Fast mode - 90 180 ns Changes for VACM=VDDANA/2 100mV overdrive, Low power mode 282 520 ns Enable to ready delay Fast mode - 1 2.
PAGE 1057
SAM D21 Family Electrical Characteristics at 105°C ...........continued Symbol RetEEPROM10k CycEEPROM 1. 2. Parameter Conditions Retention after up to 10k Average ambient 55°C Cycling Endurance(2) -40°C < Ta < 105°C Min. Typ. Max. Units 20 100 - Years 100k 600k - Cycles The EEPROM emulation is a software emulation described in the App note AT03265. An endurance cycle is a write and an erase operation. 38.8 Oscillators Characteristics 38.8.
PAGE 1058
SAM D21 Family Electrical Characteristics at 105°C ...........continued Symbol Parameter Conditions Min. Typ. Max. Units CXIN Parasitic capacitor load - 5.9 - pF CXOUT Parasitic capacitor load - 3.
PAGE 1059
SAM D21 Family Electrical Characteristics at 105°C Figure 38-4. Crystal Oscillator Connection Xin C LEXT Crystal LM C SHUNT RM C STRAY CM Xout C LEXT 38.8.2 External 32 kHz Crystal Oscillator (XOSC32K) Characteristics 38.8.2.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin. Table 38-23. Digital Clock Characteristics Symbol Parameter fCPXIN32 Conditions Min. Typ. Max.
PAGE 1060
SAM D21 Family Electrical Characteristics at 105°C ...........continued Symbol Parameter Conditions IXOSC32K Current consumption ESR 38.8.3 Crystal equivalent series resistance f=32.768kHz Safety Factor = 3 CL=12.5pF Min. Typ. Max. Units - 1.22 2.2 μA - - 100 kΩ Digital Frequency Locked Loop (DFLL48M) Characteristics Table 38-25. DFLL48M Characteristics - Open Loop Mode Symbol Parameter Conditions Min. Typ. Max. Units fOUT Output frequency IDFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.
PAGE 1061
SAM D21 Family Electrical Characteristics at 105°C 38.8.4 32.768kHz Internal oscillator (OSC32K) Characteristics Table 38-27. 32kHz RC Oscillator Characteristics Symbol Parameter Conditions fOUT Calibrated against a 32.768kHz reference at 25°C, over [-40, +125]C, over [1.62, 3.63]V 28.508 32.768 35.132 Calibrated against a 32.768kHz reference at 25°C, at VDD=3.3V 32.276 32.768 33.260 Calibrated against a 32.768kHz reference at 25°C, over [1.62, 3.63]V 31.457 32.768 34.
PAGE 1062
SAM D21 Family Electrical Characteristics at 105°C ...........continued Symbol Parameter TempCo Frequency vs. temperature drift Conditions Min. Typ. Max. Units SupplyCo Frequency vs. supply drift 38.8.7 -1.2 1 -2 2 IOSC8M Current consumption IIDLEIDLE2 on OSC32K versus IDLE2 on calibrated OSC8M enabled at 8MHz (FRANGE=1, PRESC=0) - 64 96 μA tSTARTUP Startup time I - 2.4 3.
PAGE 1063
SAM D21 Family Electrical Characteristics at 105°C ...........continued Symbol Parameter Conditions Min. Typ. Max. Units Jp Period jitter fIN= 32 kHz, fOUT= 48 MHz - 2.1 3.0 fIN= 32 kHz, fOUT= 96 MHz - 3.8 9.2 fIN= 2 MHz, fOUT= 48 MHz - 2.2 3.2 fIN= 2 MHz, fOUT= 96 MHz - 4.4 10.0 After startup, time to get lock signal. fIN= 32 kHz, fOUT= 96 MHz - 1.2 2 ms fIN= 2 MHz, fOUT= 96 MHz - 25 50 μs - 40 50 60 % tLOCK Duty Lock Time Duty cycle % Note: 1.
PAGE 1064
SAM D21 Family Electrical Characteristics at 105°C Table 38-32. Power Consumption Symbol Parameters Drift Calibration PTC scan rate Oversamples (msec) 10 50 Disabled 100 200 IDD Current Consumption 10 50 Enabled 100 200 38.10 Ta Typ.
PAGE 1065
SAM D21 Family Electrical Characteristics at 125°C 39. Electrical Characteristics at 125°C 39.1 Disclaimer All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid across operating temperature and voltage unless otherwise specified. 39.2 Absolute Maximum Ratings Stresses beyond those listed in the table below may cause permanent damage to the device.
PAGE 1066
SAM D21 Family Electrical Characteristics at 125°C Notes: 1. With BOD33 disabled. If the BOD33 is enabled, check Table 37-21. 39.4 Maximum Clock Frequencies Table 39-3. Maximum GCLK Generator Output Frequencies (Device Variant A) Symbol Description Conditions Max. Units fGCLKGEN0 / fGCLK_MAIN fGCLKGEN1 GCLK Generator Output Frequency Undivided 96 MHz Divided 32 MHz fGCLKGEN2 fGCLKGEN3 fGCLKGEN4 fGCLKGEN5 fGCLKGEN6 fGCLKGEN7 fGCLKGEN8 Table 39-4.
PAGE 1067
SAM D21 Family Electrical Characteristics at 125°C ...........continued Symbol Description Max.
PAGE 1068
SAM D21 Family Electrical Characteristics at 125°C Table 39-5. Maximum GCLK Generator Output Frequencies (Device Variant B, C, D, and L) Symbol Description Conditions Max. Units fGCLKGEN0 / fGCLK_MAIN fGCLKGEN1 GCLK Generator Output Frequency Undivided 96 MHz Divided 48 MHz fGCLKGEN2 fGCLKGEN3 fGCLKGEN4 fGCLKGEN5 fGCLKGEN6 fGCLKGEN7 fGCLKGEN8 Table 39-6. Maximum Peripheral Clock Frequencies (Device Variant B, C, D, and L) Symbol Description Max.
PAGE 1069
SAM D21 Family Electrical Characteristics at 125°C ...........continued 39.5 Symbol Description Max.
PAGE 1070
SAM D21 Family Electrical Characteristics at 125°C • • • • • • • – XOSC (crystal oscillator) stopped – XOSC32K (32 kHz crystal oscillator) running with external 32kHz crystal – DFLL48M using XOSC32K as reference and running at 48 MHz Clocks – DFLL48M used as main clock source, except otherwise specified – CPU, AHB clocks undivided – APBA clock divided by 4 – APBB and APBC bridges off The following AHB module clocks are running: NVMCTRL, APBA bridge – All other AHB clocks stopped The following peripheral
PAGE 1071
SAM D21 Family Electrical Characteristics at 125°C Table 39-7. Current Consumption (Device Variant A, B, C and L. Silicon Revision F) • Mode Conditions TA Typ. Max. Units ACTIVE CPU running a While(1) algorithm 125°C 3.75 4.12 mA CPU running a While(1) algorithm VDDIN=1.8V, CPU is running on Flash with 3 wait states 125°C 3.77 4.
PAGE 1072
SAM D21 Family Electrical Characteristics at 125°C ...........continued Mode Conditions TA STANDBY XOSC32K running , RTC running at 1kHz(1) Max. Units 125°C 348.0 850.0 μA (Device Variant B, Die Revision E) XOSC32K and RTC stopped(1) 125°C 346.0 848.0 STANDBY XOSC32K running , RTC running at 1kHz(1) 125°C 294.0 782.0 XOSC32K and RTC stopped(1) 125°C 292.0 780.0 (Device Variant B and C, Die Revision F) Typ. μA Note: 1. Measurements were done with SYSCTRL->VREG.bit.
PAGE 1073
SAM D21 Family Electrical Characteristics at 125°C Table 39-9. Wake-up Time (SAMD21) Mode Conditions TA Min. Typ. Max. Units IDLE0 OSC8M used as main clock source, Cache disabled 125°C 3.9 IDLE1 OSC8M used as main clock source, Cache disabled 125°C 13.5 14.9 16.4 IDLE2 OSC8M used as main clock source, Cache disabled 125°C 14.4 15.8 17.2 STANDBY OSC8M used as main clock source, Cache disabled 125°C 19.2 20.6 22.1 4.0 4.1 μs Figure 39-1.
PAGE 1074
SAM D21 Family Electrical Characteristics at 125°C VDD Figure 39-2. POR Operating Principle VPOT+ VPOT- Reset Time 39.6.2 Brown-Out Detectors Characteristics 39.6.2.1 BOD33 Table 39-11. BOD33 Characteristics (Device Variant A) Symbol Parameter Conditions Temp. Step size, between adjacent values in BOD33.LEVEL Min. Typ. Max. Units - 34 - mV 170 mV VHYST VBOD+ - VBOD- Hysteresis ON 35 - tDET Detection time Time with VDDANA < VTH necessary to generate a reset signal - 0.
PAGE 1075
SAM D21 Family Electrical Characteristics at 125°C ...........continued Symbol Parameter ISbyBOD33 Current consumption in Standby mode Conditions Temp. Min. Typ. Sampling mode 25°C - 0.132 0.38 μA -40 to 125°C - - - 1.2(1) - tSTARTUP Start-up time Max. Units 1.62 μs Note: 1. These values are based on simulation. These values are not covered by test limits in production or characterization. Table 39-12.
PAGE 1076
SAM D21 Family Electrical Characteristics at 125°C ...........continued Symbol Parameter Conditions Min. Typ. Max. Units Sample rate(1) Single shot (with VDDANA > 3.0V) 5 - 300 ksps 5 - 350 ksps 0.5 - - cycles - 6 - cycles Voltage reference range 1.0 - VDDANA-0.6 V Internal 1V reference - 1.0 - V - VDDANA/ 1.
PAGE 1077
SAM D21 Family Electrical Characteristics at 125°C 4. All single-shot measurements are performed with VDDANA > 3.0V. Table 39-14. Operating Conditions (Device Variant B, C, D and L) Symbol Parameter Conditions Min. Typ. Max. Units VDDANA Power Supply Voltage T>105°C 3 - 3.6 V RES Resolution 8 - 12 bits fCLK_ADC ADC Clock frequency 30 - 2100 kHz Conversion speed 10 1000 ksps Sample rate(1) Single shot 5 - 300 ksps Free running 5 - 350 ksps 0.
PAGE 1078
SAM D21 Family Electrical Characteristics at 125°C 1. 2. 3. These values are based on characterization. These values are not covered by test limits in production. These values are based on simulation. These values are not covered by test limits in production or characterization. In this condition and for a sample rate of 350ksps, 1 Conversion at gain 1x takes 6 clock cycles of the ADC clock (conditions: 1X gain, 12-bit resolution, differential mode, free-running). Table 39-15.
PAGE 1079
SAM D21 Family Electrical Characteristics at 125°C ...........continued Symbol Parameter Gain Accuracy(5) Offset Error SFDR Spurious Free Dynamic Range SINAD Signal-to-Noise and Distortion SNR THD Signal-to-Noise Ratio Total Harmonic Distortion Noise RMS Conditions Min. Ext. Ref. 0.5x +/-0.005 +/-0.05 +/-0.15 % Ext. Ref. 2x to 16x +/-0.01 +/-0.03 +/-0.5 % Ext. Ref. 1x -8.0 -1.0 +8.0 mV VREF=VDDANA/1.48 -8.0 -0.6 +8.0 mV Bandgap -6.0 -1.0 +8.0 mV 1x Gain FCLK_ADC = 2.1MHz 65.
PAGE 1080
SAM D21 Family Electrical Characteristics at 125°C ...........continued Symbol Parameter Conditions Min. Typ. Ext. Ref. 0.5x +/-0.1 +/-0.34 +/-0.4 Ext. Ref. 2x to 16X +/-0.01 +/-0.1 +/-0.15 % Offset Error Ext. Ref. 1x -5.0 1.5 +10.0 mV SFDR Spurious Free Dynamic Range 63.1 65.0 66.5 dB SINAD Signal-to-Noise and Distortion 1x Gain FCLK_ADC = 2.1MHz 50.7 59.5 61.0 dB SNR Signal-to-Noise Ratio 49.9 60.0 64.0 dB -65.4 -63.0 -62.1 dB - 1.
PAGE 1081
SAM D21 Family Electrical Characteristics at 125°C 4. 39.6.4 The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (Vref/GAIN) Inputs and Sample and Hold Acquisition Times The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in order to achieve maximum accuracy. Seen externally the ADC input consists of a resistor (�SAMPLE) and a capacitor (�SAMPLE).
PAGE 1082
SAM D21 Family Electrical Characteristics at 125°C ...........continued Symbol Parameter Conditions Maximum capacitance load IDD DC supply current(2) Voltage pump disabled Min. Typ. Max. Units - - 100 pF - 160 242 μA Min. Typ. Max. Units Table 39-20. Operating Conditions(1)(Device Variant B, C, D and L) Symbol Parameter Conditions VDDANA Analog supply voltage 1.62 - 3.63 V AVREF External reference voltage 1.0 - VDDANA-0.
PAGE 1083
SAM D21 Family Electrical Characteristics at 125°C ...........continued Symbol Parameter Conditions INL Integral non-linearity VREF= Ext 1.0V VREF = VDDANA VREF= INT1V DNL Differential non-linearity VREF= Ext 1.0V VREF= VDDANA VREF= INT1V Min. Typ. Max. Units VDD = 1.6V 0.75 1.1 2.0 LSB VDD = 3.6V 0.6 1.2 2.5 VDD = 1.6V 1.4 2.2 3.5 VDD = 3.6V 0.9 1.4 1.5 VDD = 1.6V 0.75 1.3 2.5 VDD = 3.6V 0.8 1.2 1.5 VDD = 1.6V +/-0.9 +/-1.2 +/-2.0 VDD = 3.6V +/-0.9 +/-1.
PAGE 1084
SAM D21 Family Electrical Characteristics at 125°C 1. All values measured using a conversion rate of 350ksps. 39.6.6 Analog Comparator Characteristics Table 39-24. Electrical and Timing (Device Variant A) Symbol Parameter Min. Typ. Max. Positive input voltage range 0 - VDDANA V Negative input voltage range 0 - VDDANA Hysteresis = 0, Fast mode -15 0.0 +15 mV Hysteresis = 0, Low power mode -25 0.
PAGE 1085
SAM D21 Family Electrical Characteristics at 125°C ...........continued Symbol Parameter Conditions Min. Typ. Max. Units Changes for VACM=VDDANA/2 100mV overdrive, Fast mode - 90 180 ns Changes for VACM=VDDANA/2 100mV overdrive, Low power mode 282 520 ns Enable to ready delay Fast mode - 1 2.6 μs Enable to ready delay Low power mode - 14 22 μs INL(3) - 0.75 +1.58 LSB DNL(3) - 0.25 +0.95 LSB Offset Error (1)(2) -0.200 0.260 +1.035 LSB Gain Error (1)(2) 0.
PAGE 1086
SAM D21 Family Electrical Characteristics at 125°C ...........continued Symbol Parameter Conditions Min. Typ. Max. Units Variation over VDDANA VDDANA=1.62V to 3.6V voltage -0.4 3 Temperature Sensor accuracy -13.0 - Using the method described in the 37.11.8.2 Software-based Refinement of the Actual Temperature 1.4 mV/V 13.0 °C Note: 1. These values are based on characterization. These values are not covered by test limits in production. 39.7 NVM Characteristics Table 39-28.
PAGE 1087
SAM D21 Family Electrical Characteristics at 125°C 39.8 Oscillators Characteristics 39.8.1 Crystal Oscillator (XOSC) Characteristics 39.8.1.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN. Table 39-31. Digital Clock Characteristics Symbol Parameter fCPXIN XIN clock frequency Conditions Min. Typ. Max. Units - - 32 MHz 39.8.1.
PAGE 1088
SAM D21 Family Electrical Characteristics at 125°C ...........continued Symbol Parameter Current Consumption Conditions Min. Typ. Max.
PAGE 1089
SAM D21 Family Electrical Characteristics at 125°C ...........continued Symbol Parameter Conditions Min. Typ. Max. Units ESR f = 0.455 MHz, CL = 100pF XOSC.GAIN = 0 - - 5.6K Ω f = 2MHz, CL = 20pF XOSC.GAIN = 0 - - 416 f = 4MHz, CL = 20pF XOSC.GAIN = 1 - - 243 f = 8 MHz, CL = 20pF XOSC.GAIN = 2 - - 138 f = 16 MHz, CL = 20pF XOSC.GAIN = 3 - - 66 f = 32MHz, CL = 18pF XOSC.
PAGE 1090
SAM D21 Family Electrical Characteristics at 125°C Figure 39-4. Oscillator Connection Xin C LEXT Crystal LM C SHUNT RM C STRAY CM Xout C LEXT 39.8.2 External 32 kHz Crystal Oscillator (XOSC32K) Characteristics 39.8.2.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin. Table 39-34. Digital Clock Characteristics Symbol Parameter fCPXIN32 Conditions Min. Typ. Max. Units XIN32 clock frequency - 32.
PAGE 1091
SAM D21 Family Electrical Characteristics at 125°C ...........continued Symbol Parameter ESR Conditions Crystal equivalent series resistance CL=12.5pF f=32.768kHz , Safety Factor = 3 Min. Typ. Max. Units - 141 - kΩ Table 39-36. 32kHz Crystal Oscillator Characteristics (Device Variant B, C, D and L) Symbol Parameter fOUT Conditions Crystal oscillator frequency tSTARTUP Startup time 39.8.3 ESRXTAL = 39.9 kΩ, CL = 12.5 pF Min. Typ. Max.
PAGE 1092
SAM D21 Family Electrical Characteristics at 125°C ...........continued Symbol Parameter Conditions Min. Typ. Max. Units IDFLL IDFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 - 403 453 μA DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 - 8 μs Power consumption on VDDIN tSTARTUP Start-up time 9 fOUT within 90 % of final value Note: 1. DFLL48M in Open loop after calibration at room temperature. Table 39-39.
PAGE 1093
SAM D21 Family Electrical Characteristics at 125°C ...........continued Symbol Parameter Conditions Min. Typ. Max. Units tLOCK fREF = 32 .768kHz DFLLVAL.COARSE = DFLL48M COARSE CAL - 200 500 Typ. Max. Lock time μs DFLLVAL.FINE = 512 DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10 39.8.4 32.768kHz Internal oscillator (OSC32K) Characteristics Table 39-41. 32kHz RC Oscillator Characteristics (Device Variant A) Symbol Parameter Conditions Min.
PAGE 1094
SAM D21 Family Electrical Characteristics at 125°C 39.8.5 Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics Table 39-43. Ultra Low Power Internal 32kHz RC Oscillator Characteristics (Device Variant A) Symbol Parameter Conditions Min. Typ. Max. fOUT Output frequency Calibrated against a 32.768kHz 25.559 32.768 40.305 kHz reference at 25°C, over [-40, +85]C, over [1.62, 3.63]V Calibrated against a 32.768kHz reference at 25°C, at VDD=3.3V 31.293 32.768 34.
PAGE 1095
SAM D21 Family Electrical Characteristics at 125°C 39.8.6 8MHz RC Oscillator (OSC8M) Characteristics Table 39-45. Internal 8MHz RC Oscillator Characteristics (Device Variant A) Symbol Parameter Conditions fOUT Calibrated against a 8MHz reference at 25°C, 7.54 8 over [-40, +85]°C, over [1.62, 3.63]V 8.19 MHz Calibrated against a 8MHz reference at 25°C, 7.94 8 at VDD=3.3V 8.06 Calibrated against a 8MHz reference at 25°C, 7.92 8 over [1.62, 3.63]V 8.08 IOSC8M Output frequency Min. Typ. Max.
PAGE 1096
SAM D21 Family Electrical Characteristics at 125°C ...........continued Symbol Parameter Conditions Min. Typ. Max. Units Jp Period jitter fIN= 32 kHz, fOUT= 48 MHz - 1.5 2.0 fIN= 32 kHz, fOUT= 96 MHz - 3.0 10.0 fIN= 2 MHz, fOUT= 48 MHz - 1.3 2.0 fIN= 2 MHz, fOUT= 96 MHz - 3.0 7.0 After start-up, time to get lock signal. fIN= 32 kHz, fOUT= 96 MHz - 1.3 2 ms fIN= 2 MHz, fOUT= 96 MHz - 25 50 μs 40 50 60 % tLOCK Duty Lock Time Duty cycle % Table 39-48.
PAGE 1097
SAM D21 Family Electrical Characteristics at 125°C ...........continued Symbol Parameter Conditions Min. Typ. Max. Units Jp Period jitter fIN= 32 kHz, fOUT= 48 MHz - 2.1 3.2 fIN= 32 kHz, fOUT= 96 MHz - 3.8 9.2 fIN= 2 MHz, fOUT= 48 MHz - 2.2 3.4 fIN= 2 MHz, fOUT= 96 MHz - 5.0 10.5 After start-up, time to get lock signal. fIN= 32 kHz, fOUT= 96 MHz - 1.2 2 ms fIN= 2 MHz, fOUT= 96 MHz - 25 50 μs 40 50 60 % tLOCK Duty Lock Time Duty cycle % Note: 1.
PAGE 1098
SAM D21 Family Electrical Characteristics at 125°C Table 39-50. Power Consumption (1) Symbol Parameters Drift Calibration PTC scan rate Oversamples (msec) 10 50 Disabled 100 200 IDD (2) Current Consumption 10 50 Enabled 100 200 Ta Typ. Max Units 4 66 791 16 75 803 4 61 787 16 63 791 4 61 788 16 62 790 4 60 788 61 789 71 802 16 80 813 4 63 792 16 65 795 4 62 791 16 63 793 4 62 790 16 63 791 16 4 Max 125°C Typ 25°C µA Note: 1.
PAGE 1099
SAM D21 Family AEC-Q100 125°C Specifications 40. AEC-Q100 125°C Specifications 40.1 Disclaimer All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid across operating temperature and voltage unless otherwise specified. 40.2 Thermal Considerations 40.2.1 Thermal Resistance Data The following Table summarizes the thermal resistance data depending on the package. Table 40-1. Thermal Resistance Data 40.2.
PAGE 1100
SAM D21 Family AEC-Q100 125°C Specifications indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 40-2. Absolute Maximum Ratings Symbol Description Conditions Min. Max. Units VDD Power Supply Voltage 0 3.8 V IVDD Current into a VDD pin - 28 (1) mA IGND Current out of a GND pin - 39 (1) mA VPIN Pin voltage with respect to GND and VDD GND-0.3V VDD+0.
PAGE 1101
SAM D21 Family AEC-Q100 125°C Specifications Table 40-5. Supply Rates Fall Rate Rise Rate Symbol Conditions Max Max Units VDDIO VDDIN DC supply peripheral I/Os, internal regulator and analog supply voltage 0.05 0.1 V/μs VDDANA Note: To secure power up and power down sequence, enabling BOD33 is recommended. Related Links Power Supply and Start-Up Considerations 40.6 Maximum Clock Frequencies Table 40-6.
PAGE 1102
SAM D21 Family AEC-Q100 125°C Specifications ...........continued Symbol Description Max.
PAGE 1103
SAM D21 Family AEC-Q100 125°C Specifications Table 40-8. Maximum GCLK Generator Output Frequencies (Device Variant B, D) Symbol Description Conditions Max Units fGCLKGEN0 / fGCLK_MAIN GCLK Generator Output Frequency Undivided 96 MHz Divided 48 MHz fGCLKGEN1 fGCLKGEN2 fGCLKGEN3 fGCLKGEN4 fGCLKGEN5 Table 40-9. Maximum Peripheral Clock Frequencies (Device Variant B, D) Symbol Description Max.
PAGE 1104
SAM D21 Family AEC-Q100 125°C Specifications ...........continued 40.7 Symbol Description Max.
PAGE 1105
SAM D21 Family AEC-Q100 125°C Specifications • • • • • • – CPU, AHB clocks undivided – APBA clock divided by 4 – APBB and APBC bridges off The following AHB module clocks are running: NVMCTRL, APBA bridge – All other AHB clocks stopped The following peripheral clocks running: PM, SYSCTRL, RTC – All other peripheral clocks stopped I/Os are inactive with internal pull-up CPU is running on Flash with 1 wait states NVMCTRL cache enabled BOD33 disabled Table 40-10.
PAGE 1106
SAM D21 Family AEC-Q100 125°C Specifications ...........continued Mode Conditions STANDBY (1) XOSC32K running TA VCC Typ. Max. Units 25°C 3.3V 4.2 13.3 µA RTC running at 1kHz 125°C (1) 3.3V 430.6 1128.0 XOSC32K and RTC stopped 25°C 12.2 3.3V 2.9 125°C(1) 3.3V 428.6 1126.0 Note: 1. Measurements done with VREG.bit.RUNSTDBY = 1. Table 40-11. Current Consumption (Device Variant B) Mode Conditions TA Vcc Typ. Max. Units ACTIVE CPU running a While 1 algorithm 25°C 3.3V 2.7 3.
PAGE 1107
SAM D21 Family AEC-Q100 125°C Specifications ...........continued Mode Conditions STANDBY (1) XOSC32K running TA Vcc Typ. Max. Units 25°C 3,3V 61.0 83.0 µA RTC running at 1kHz 125°C 3,3V 294.0 782.0 XOSC32K and RTC stopped 25°C 82.0 3,3V 60.0 125°C 3,3V 292.0 780.0 Note: 1. Measurements done with VREG.bit.RUNSTDBY = 1. Table 40-12.
PAGE 1108
SAM D21 Family AEC-Q100 125°C Specifications ...........continued Mode Conditions STANDBY (1) Ta Vcc Typ. Max XOSC32K running RTC running at 25°C 3,3V 1kHz 125°C 3,3V 61.0 83.0 294.0 782.0 25°C 3,3V 60.0 82.0 125°C 3,3V 292.0 780.0 XOSC32K and RTC stopped Units µA Note: 1. Measurements done with VREG.bit.RUNSTDBY = 1. Table 40-13.
PAGE 1109
SAM D21 Family AEC-Q100 125°C Specifications ...........continued Symbol Parameter Conditions Min. Typ. Max. Units IOL VDD=2.7V-3V, - - - mA PORT.PINCFG.DRVSTR=0 - - 1 VDD=3V-3.63V, - - - PORT.PINCFG.DRVSTR=0 - - 2.5 VDD=2.7V-3V, - - - PORT.PINCFG.DRVSTR=1 - - 3 VDD = 3V-3.63V, - - - PORT.PINCFG.DRVSTR=1 - - 10 - - - PORT.PINCFG.DRVSTR=0 - - 0.7 VDD=3V-3.63V, - - - PORT.PINCFG.DRVSTR=0 - - 2 VDD=2.7V-3V, - - - PORT.PINCFG.DRVSTR=1 - - 2 VDD=3V-3.
PAGE 1110
SAM D21 Family AEC-Q100 125°C Specifications Table 40-15. I2C Pins Characteristics in I2C Configuration Symbol Parameter Condition Min. Typ. Max. VIL Input low-level voltage VDD = 2.7V-3.63V - - VIH Input high-level voltage VDD = 2.7V-3.63VI 0.55*VDD - - VHYS Hysteresis of Schmitt trigger inputs - 0.08*VDD - - VOL Output low-level voltage VDD> 2.0V - - - IOL = 3 mA - - 0.4 VDD≤2.0V - - - IOL = 2 mA - - 0.2*VDD Units 0.
PAGE 1111
SAM D21 Family AEC-Q100 125°C Specifications ...........continued Symbol Parameter Conditions Min. Typ. Max. Units IOL VDD = 2.7V-3V, - - - mA PORT.PINCFG.DRVSTR=0 - - 1 VDD = 3V-3.63V, - - - PORT.PINCFG.DRVSTR=0 - - 2.5 VDD = 2.7V-3V, - - - PORT.PINCFG.DRVSTR=1 - - 3 VDD = 3V-3.63V, - - - PORT.PINCFG.DRVSTR=1 - - 10 - - - PORT.PINCFG.DRVSTR=0 - - 0.7 VDD = 3V-3.63V, - - - PORT.PINCFG.DRVSTR=0 - - 2 VDD = 2.7V-3V, - - - PORT.PINCFG.
PAGE 1112
SAM D21 Family AEC-Q100 125°C Specifications ...........continued Symbol Parameter Conditions Min. Typ. Max. VIL Input low-level voltage VDD = 2.7V-3.63V - - 0.29*VDD V VIH Input high-level voltage VDD = 2.7V-3.63V 0.55*VDD - VOL Output low-level voltage VDD>2.7V, IOL max - 0.1*VDD 0.2*VDD VOH Output high-level voltage VDD>2.7V, IOH max 0.8*VDD 0.9*VDD - IOL Output low-level current VDD = 2.7V-3V, - - 3 VDD=3V-3.63V, - - 8 VDD=2.7V-3V, - - 2 VDD = 3V-3.
PAGE 1113
SAM D21 Family AEC-Q100 125°C Specifications Table 40-19. POR Characteristics (Device Variant B and D) Symbol Parameters Conditions VPOT+ Voltage threshold Level on VDDIN rising VPOT- Voltage threshold Level on VDDIN falling Min. Typ. Max. Unit 1.27 1.45 1.62 V VDD falls at 1V/ms or slower 0.53 0.99 1.32 V Figure 40-1. POR Operating Principle 40.9.2 Brown-Out Detectors (BOD) Characteristics Table 40-20. BOD33 Level Value (Device Variant A and B) Symbol BOD33.LEVEL Conditions Min. Typ. Max.
PAGE 1114
SAM D21 Family AEC-Q100 125°C Specifications Table 40-21. BOD33 Characteristics (Device Variant D) Symbol BOD33.LEVEL Conditions Min. Typ. Max. VBOD+ 34 Hysteresis ON - 2.69 2.76 VBOD- or VBOD 34 Hysteresis ON or OFF 2.51 2.59 2.66 Units V Table 40-22. BOD33 Characteristics (Device Variant A) Symbol Parameter Conditions Min. Typ. Max. Units Step size, between adjacent values in BOD33.
PAGE 1115
SAM D21 Family AEC-Q100 125°C Specifications ...........continued Symbol Parameter Conditions Min. Typ. Max. Units tSTARTUP(1) Start-up time 2.2(1) - - µs Note: 1. These values are based on simulation. These values are not covered by test limits in production or characterization. 40.9.3 Analog-to-Digital (ADC) Characteristics Table 40-24. Operating Conditions (Device Variant A) Symbol Parameters VDDANA Min Typ Max Unit Power supply voltage 2.7 - 3.
PAGE 1116
SAM D21 Family AEC-Q100 125°C Specifications ...........continued Symbol Parameters RSAMPLE Input channel source resistance(2) IDD DC supply current(1) Conditions fCLK_ADC = 2.1MHzI(3) Min Typ Max Unit - - 3.5 kohms - 1.25 3.9 mA Min Typ Max Unit Table 40-25. Operating Conditions (Device Variant B and D) Symbol Parameters VDDANA Power supply voltage 2.7 - 3.
PAGE 1117
SAM D21 Family AEC-Q100 125°C Specifications Note: 1. These values are based on characterization. These values are not covered by test limits in production. 2. These values are based on simulation. These values are not covered by test limits in production or characterization. 3. In this condition and for a sample rate of 350ksps, 1 Conversion at gain 1x takes 6 clock cycles of the ADC clock. 4. All single-shot measurements are performed with VDDANA > 3.0V (cf. ADC errata). Table 40-26.
PAGE 1118
SAM D21 Family AEC-Q100 125°C Specifications ...........continued Symbol Parameter Conditions Min. Typ. Max. Units GE Ext. Ref 1x -15 -2.4 15 mV VREF=VDDANA/1.48 -56 -14 56 mV Bandgap -36 -7 36 mV Ext. Ref. 0.5x - +/-0.1 +/-0.7 % Ext. Ref. 2x to 16x - +/-0.04 +/-0.5 % Ext. Ref. 1x -8 1.7 8 mV VREF=VDDANA/1.48 -8 1.6 9 mV Bandgap -6 1.8 8 mV Gain Error Gain Accuracy(5) OE Offset Error SFDR Spurious Free Dynamic Range 1x Gain 63.7 69.5 71.
PAGE 1119
SAM D21 Family AEC-Q100 125°C Specifications ...........continued Symbol Parameter Conditions Min. Typ. Max. DNL Differential Non-Linearity 1x gain +/-0.5 +/-0.6 +/-0.95 LSB - Gain Error Ext. Ref. 1x -10 0.7 - Gain Accuracy(4) Ext. Ref. 0.5x +/-0.1 +/-0.3 +/-0.4 Ext. Ref. 2x to 16X +/-0.01 +/-0.1 +/-0,65 % 10 Units mV % - Offset Error Ext. Ref. 1x -17 0.2 1 mV SFDR Spurious Free Dynamic Range 1x Gain 63 65 66.5 dB SINAD Signal-to-Noise and Distortion FIN = 40kHz 50.
PAGE 1120
SAM D21 Family AEC-Q100 125°C Specifications 3. 4. 40.9.4 The ADC channels on pins PA08, PA09, PA10, and PA11 are powered from the VDDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (VREF/GAIN). Digital to Analog Converter (DAC) Characteristics Table 40-30.
PAGE 1121
SAM D21 Family AEC-Q100 125°C Specifications ...........continued Symbol Parameter Conditions INL Integral non-linearity VREF= Ext 1.0V VREF = VDDANA VREF= INT1V DNL Differential non-linearity VREF= Ext 1.0V VREF= VDDANA VREF= INT1V Min. Typ. Max. Units VDD = 2.7V - 1.2 1.5 LSB VDD = 3.6V - 1.2 1.5 VDD = 2.7V - 1.4 1.5 VDD = 3.6V - 1.4 1.5 VDD = 2.7V - 1.2 2 VDD = 3.6V - 1.2 2 VDD = 2.7V - +/-1.2 +/-1.6 VDD = 3.6V - +/-1.1 +/-1.5 VDD = 2.7V - +-1.3 +/-1.
PAGE 1122
SAM D21 Family AEC-Q100 125°C Specifications Note: 1. All values measured using a conversion rate of 350ksps. 40.9.5 Analog Comparator Characteristics Table 40-34. Electrical and Timing (Device Variant A) Symbol Parameter Conditions Min. Typ. Max.
PAGE 1123
SAM D21 Family AEC-Q100 125°C Specifications ...........continued Symbol Parameter Conditions Min. Typ. Max. - Propagation delay Changes for VACM=VDDANA/2 - 90 180 - 282 534 - 1 3 - 14 23 0.75 1.6 100mV overdrive, Fast mode Changes for VACM=VDDANA/2 100mV overdrive, Low power mode tSTARTUP Startup time Enable to ready delay Fast mode Enable to ready delay Low power mode VSCALE INL(3) - -1.6 DNL(3) - -0.95 0.25 0.95 Offset Error (1)(2) - -0.2 1.
PAGE 1124
SAM D21 Family AEC-Q100 125°C Specifications Table 40-38. Maximum Operating Frequency (Device Variant B and D) VDD range NVM Wait States Maximum Operating Frequency Units 2.7V to 3.63V 0 24 MHz 1 48 Note: With on this flash technology, a max number of 8 consecutive write is allowed per row. Once this number is reached, a row erase is mandatory. Table 40-39. Flash Endurance and Data Retention (Device Variant A) Symbol Parameter Conditions Min. Typ. Max.
PAGE 1125
SAM D21 Family AEC-Q100 125°C Specifications Note: 1. The EEPROM emulation is a software emulation described in the Application Note AT03265: SAM D10/D11/D20/D21/R/L/C EEPROM Emulator (EEPROM) Service. 2. An endurance cycle is a write and an erase operation. Table 40-43. NVM Characteristics 40.11 Symbol Parameter Conditions Min. Typ. Max. Units tFPP Page programming time - - - 2.
PAGE 1126
SAM D21 Family AEC-Q100 125°C Specifications ...........continued Symbol Parameter Conditions Min. Typ. Max. Units IXOSC f = 2MHz, CL=20 pF XOSC.GAIN=0, AGC off - 65 240 uA f = 2MHz, CL=20 pF XOSC.GAIN=0, AGC on - 52 240 f = 4MHz, CL=20 pF XOSC.GAIN=1, AGC off - 117 309 f = 4MHz, CL=20 pF XOSC.GAIN=1, AGC on - 74 281 f = 8MHz, CL=20 pF XOSC.GAIN=2, AGC off - 226 435 f = 8MHz, CL=20 pF XOSC.GAIN=2, AGC on - 128 356 f = 16MHz, CL=20 pF XOSC.
PAGE 1127
SAM D21 Family AEC-Q100 125°C Specifications Figure 40-2. Oscillator Connection 40.11.2 External 32 kHz Crystal Oscillator (XOSC32K) Characteristics Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin. Table 40-46. Digital Clock Characteristics Symbol Parameter Conditions Min. Typ. Max Units fCPXIN32 XIN32 clock frequency digital mode - 32.
PAGE 1128
SAM D21 Family AEC-Q100 125°C Specifications Table 40-47. 32 kHz Crystal Oscillator Electrical Characteristics (Device Variant A) Symbol Parameter Conditions Min. Typ. fOUT - - Crystal oscillator frequency Max Units 32768 - Hz tSTARTUP Startup time ESRXTAL = 39.9 kΩ, CL = 12.5 pF 28K 31K cycles CL Crystal load capacitance - - - 12.5 pF CSHUNT Crystal shunt capacitance - - 0.1 - pF CXIN32 Parasitic capacitor load TQFP64/48/32 packages - 3.1 - pF - 3.
PAGE 1129
SAM D21 Family AEC-Q100 125°C Specifications ...........continued Symbol Parameter Conditions fOUT DFLLVAL.COARSE = DFLL48M COARSE CAL 46.5 48 Output frequency Min. Typ. Max. Units 49 MHz DFLLVAL.FINE = 512 at 25°C, over [2.7, 3.6]V IDFLL Power consumption DFLLVAL.COARSE = DFLL48M COARSE CAL on VDDIN DFLLVAL.FINE = 512 tSTARTUP Startup time DFLLVAL.COARSE = DFLL48M COARSE CAL - 403 457 µA 8 µs 12 DFLLVAL.FINE = 512 fOUT within 90 % of final value Table 40-50.
PAGE 1130
SAM D21 Family AEC-Q100 125°C Specifications fREF Reference frequency - Jitter Cycle to Cycle jitter fREF = XTAL, 32 .768kHz, 100ppm 0.732 32.768 33 kHz - - 0.42 ns µA DFLLMUL = 1464 IDFLL Power consumption on VDDIN fREF = XTAL, 32 .768kHz, 100ppm - 403 457 tLOCK Lock time fREF = XTAL, 32 .768kHz, 100ppm - 350 1500 µs DFLLMUL = 1464 DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10 Table 40-52.
PAGE 1131
SAM D21 Family AEC-Q100 125°C Specifications ...........continued Symbol Parameter Conditions Min. Typ. Max. Units tLOCK fREF = XTAL, 32 .768kHz, 100ppm - 350 1500 µs Lock time DFLLMUL = 1464 DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10 Note: All parts are tested in production to be able to use the DFLL as main CPU clock whether in DFLL closed loop mode with an external OSC reference or the internal OSC8M. 40.
PAGE 1132
SAM D21 Family AEC-Q100 125°C Specifications Table 40-54. 32 kHz RC Oscillator Electrical Characteristics (Device Variant B and D) Symbol Parameter Conditions Min. fOUT Calibrated against a 32.768kHz 26.214 32.768 39.321 kHz Output frequency Typ. Max Units reference at 25°C, over [-40, +125]C, over [2.7, 3.63]V Calibrated against a 32.768kHz reference at 25°C, at VDD=3.3V 32.113 32.768 33.423 kHz Calibrated against a 32.768kHz 31.457 32.768 34.079 kHz reference at 25°C, over [2.7, 3.
PAGE 1133
SAM D21 Family AEC-Q100 125°C Specifications 40.11.6 8MHz RC Oscillator (OSC8M) Characteristics Table 40-56. Internal RC Oscillator Electrical Characteristics (Device Variant A) Symbol Parameter Conditions Min. Typ. Max Units fOUT Calibrated against a 8MHz reference at 25°C, over [-10, +70]C, over [2.7, 3.6]V 7.84 8 8.16 MHz Calibrated against a 8MHz reference at 25°C, over [-10, +125]C, over [2.7, 3.6]V 7.8 8 8.2 Calibrated against a 8MHz reference at 25°C, over [-40, +125]C, over [2.7, 3.
PAGE 1134
SAM D21 Family AEC-Q100 125°C Specifications ...........continued Symbol Parameter Conditions Min. Typ. Max. Units IFDPLL96M Current consumption fIN= 32 kHz, fOUT= 48 MHz - 500 700 fIN= 32 kHz, fOUT= 64 MHz - 900 1200 fIN= 32 kHz, fOUT= 48 MHz - 1.5 4 fIN= 32 kHz, fOUT= 64 MHz - 2.8 7 fIN= 2 MHz, fOUT= 48 MHz - 1.3 5 fIN= 2 MHz, fOUT= 64 MHz - 3.3 8 After startup, time to get lock signal. - 1.
PAGE 1135
SAM D21 Family AEC-Q100 125°C Specifications Operating conditions VDD = 3.3 V Clocks OSC8M used as main clock source, running undivided at 8 MHz. CPU is running on Flash with '0' wait states, at 8 MHz. PTC running at 4 MHz. PTC configuration Mutual-Capacitance mode. One-touch channel. System configuration Standby Sleep mode enabled. RTC running on OSCULP32K: Used to define the PTC scan rate through the event system. Drift Calibration disabled: No interrupts, PTC scans are performed in Standby mode.
PAGE 1136
SAM D21 Family AEC-Q100 125°C Specifications Table 40-60. Power Consumption (1)(2) (Variant A) Symbol Parameters Drift Calibration PTC scan rate Oversamples Ta (msec) IDD(2) Disabled 10 Current Consumption 50 100 200 Enabled 10 50 100 200 © 2018 Microchip Technology Inc. Typ. Max. Units 4 Max. 125°C 72 1151 µA 16 Typ.
PAGE 1137
SAM D21 Family AEC-Q100 125°C Specifications Table 40-61. Power Consumption (1)(2) (Variant B and D) Symbol Parameters Drift Calibration PTC scan rate Oversamples Ta (msec) IDD(2) Disabled 10 Current Consumption 50 100 200 Enabled 10 50 100 200 Typ. Max. Units 4 Max. 125°C 66 791 16 Typ. 25°C 75 803 4 61 787 16 63 791 4 61 788 16 62 790 4 60 788 16 61 789 4 71 802 16 80 813 4 63 792 16 65 795 4 62 791 16 63 793 4 62 790 16 63 791 µA Note: 1.
PAGE 1138
SAM D21 Family Packaging Information 41. Packaging Information 41.1 Package Drawings Note: For current package drawings, refer to the Microchip Packaging Specification, which is available at http://www.microchip.com/packaging. 41.1.1 64 pin TQFP © 2018 Microchip Technology Inc.
PAGE 1139
SAM D21 Family Packaging Information Table 41-1. Device and Package Maximum Weight 300 mg Table 41-2. Package Characteristics Moisture Sensitivity Level MSL3 Table 41-3. Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification E3 © 2018 Microchip Technology Inc.
PAGE 1140
SAM D21 Family Packaging Information 41.1.2 64 pin QFN Note: The exposed die attach pad is not connected electrically inside the device. Table 41-4. Device and Package Maximum Weight 200 © 2018 Microchip Technology Inc.
PAGE 1141
SAM D21 Family Packaging Information Table 41-5. Package Charateristics Moisture Sensitivity Level MSL3 Table 41-6. Package Reference JEDEC Drawing Reference MO-220 JESD97 Classification E3 © 2018 Microchip Technology Inc.
PAGE 1142
SAM D21 Family Packaging Information 41.1.3 64 Lead QFN with Sawn Wettable Flanks Table 41-7. Device and Package Maximum Weight 200 © 2018 Microchip Technology Inc.
PAGE 1143
SAM D21 Family Packaging Information Table 41-8. Package Characteristics Moisture Sensitivity Level MSL3 Table 41-9. Package Reference JEDEC Drawing Reference MO-220 JESD97 Classification E3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. 41.1.4 64-ball UFBGA Table 41-10. Device and Package Maximum Weight 27.4 © 2018 Microchip Technology Inc.
PAGE 1144
SAM D21 Family Packaging Information Table 41-11. Package Characteristics Moisture Sensitivity Level MSL3 Table 41-12. Package Reference 41.1.5 JEDEC Drawing Reference MO-220 JESD97 Classification E8 48 pin TQFP © 2018 Microchip Technology Inc.
PAGE 1145
SAM D21 Family Packaging Information Table 41-13. Device and Package Maximum Weight 140 mg Table 41-14. Package Characteristics Moisture Sensitivity Level MSL3 Table 41-15. Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification E3 © 2018 Microchip Technology Inc.
PAGE 1146
SAM D21 Family Packaging Information 41.1.6 48 pin QFN Note: The exposed die attach pad is not connected electrically inside the device. Table 41-16. Device and Package Maximum Weight 140 mg Table 41-17. Package Characteristics Moisture Sensitivity Level MSL3 © 2018 Microchip Technology Inc.
PAGE 1147
SAM D21 Family Packaging Information Table 41-18. Package Reference 41.1.7 JEDEC Drawing Reference MO-220 JESD97 Classification E3 48 lead QFN with Sawn Wettable Flanks © 2018 Microchip Technology Inc.
PAGE 1148
SAM D21 Family Packaging Information Table 41-19. Device and Package Maximum Weight 140 mg Table 41-20. Package Characteristics Moisture Sensitivity Level MSL3 Table 41-21. Package Reference JEDEC Drawing Reference MO-220 JESD97 Classification E3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. © 2018 Microchip Technology Inc.
PAGE 1151
SAM D21 Family Packaging Information Table 41-22. Device and Package Maximum Weight 7.3 © 2018 Microchip Technology Inc.
PAGE 1152
SAM D21 Family Packaging Information Table 41-23. Package Characteristics Moisture Sensitivity Level MSL1 Table 41-24. Package Reference 41.1.9 JEDEC Drawing Reference MO-220 JESD97 Classification E1 32 pin TQFP © 2018 Microchip Technology Inc.
PAGE 1153
SAM D21 Family Packaging Information Table 41-25. Device and Package Maximum Weight 100 mg Table 41-26. Package Charateristics Moisture Sensitivity Level MSL3 Table 41-27. Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification E3 © 2018 Microchip Technology Inc.
PAGE 1154
SAM D21 Family Packaging Information 41.1.10 32 pin QFN Note: The exposed die attach pad is connected inside the device to GND and GNDANA. Table 41-28. Device and Package Maximum Weight 90 mg Table 41-29. Package Characteristics Moisture Sensitivity Level MSL3 © 2018 Microchip Technology Inc.
PAGE 1155
SAM D21 Family Packaging Information Table 41-30. Package Reference JEDEC Drawing Reference MO-220 JESD97 Classification E3 41.1.11 32 lead QFN with Sawn Wettable Flanks © 2018 Microchip Technology Inc.
PAGE 1156
SAM D21 Family Packaging Information Table 41-31. Device and Package Maximum Weight 90 mg Table 41-32. Package Characteristics Moisture Sensitivity Level MSL3 Table 41-33. Package Reference JEDEC Drawing Reference MO-220 JESD97 Classification E3 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. © 2018 Microchip Technology Inc.
PAGE 1157
SAM D21 Family Packaging Information 41.1.12 35 ball WLCSP (Device Variant B) 35-Ball Wafer Level Chip Scale Package (FQB) - 2.821x2.529 mm Body [WLCSP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B NOTE 1 1 2 3 4 5 6 A B C E D (DATUM B) E (DATUM A) 2X 0.03 C F 2X TOP VIEW 0.03 C SEE DETAIL A C SEATING PLANE A SIDE VIEW D1 1 2 3 4 5 6 F e 2 E D E1 C B A NOTE 1 e 35X Øb 0.15 0.
PAGE 1158
SAM D21 Family Packaging Information 35-Ball Wafer Level Chip Scale Package (FQB) - 2.821x2.529 mm Body [WLCSP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (A3) 0.10 C A2 A1 35X 0.
PAGE 1159
SAM D21 Family Packaging Information 14-Ball Wafer Level Chipscale Package (CS) - 1.57X2.36 Body [WLCSP] - PIC16LF1823 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D 1 NOTE 1 2 A 3 B 4 A B C E D E 2X 0.15 C 2X 0.15 C C TOP VIEW A2 A SEATING PLANE 14X A1 SIDE VIEW 0.08 C eD E eE D C B A 1 2 3 4 14X Øb 0.10 0.
PAGE 1160
SAM D21 Family Packaging Information Table 41-34. Device and Package Maximum Weight 6.2 mg Table 41-35. Package Characteristics Moisture Sensitivity Level MSL1 Table 41-36. Package Reference JEDEC Drawing Reference MO-220 JESD97 Classification E1 © 2018 Microchip Technology Inc.
PAGE 1161
SAM D21 Family Packaging Information 41.1.13 35 ball WLCSP (Device Variant C) Table 41-37. Device and Package Maximum Weight 6.22 mg Table 41-38. Package Characteristics Moisture Sensitivity Level MSL1 © 2018 Microchip Technology Inc.
PAGE 1162
SAM D21 Family Packaging Information Table 41-39. Package Reference 41.2 JEDEC Drawing Reference N/A JESD97 Classification e1 Soldering Profile The following table gives the recommended soldering profile from J-STD-20. Table 41-40. Recommended Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to peak) 3°C/s max.
PAGE 1163
SAM D21 Family Schematic Checklist 42. 42.1 Schematic Checklist Introduction This chapter describes a common checklist which should be used when starting and reviewing the schematics for a SAM D21 design. This chapter illustrates a recommended power supply connection, how to connect external analog references, programmer, debugger, oscillator and crystal. 42.1.
PAGE 1164
SAM D21 Family Schematic Checklist Table 42-1. Power Supply Connections, VDDCORE From Internal Regulator Signal Name Recommended Pin Connection Description VDDIO Digital supply voltage 1.62V - 3.63V Decoupling/filtering capacitors 100nF(1)(2) and 10μF(1) Decoupling/filtering inductor 10μH(1)(3) VDDANA 1.62V - 3.63V Decoupling/filtering capacitors 100nF(1)(2) and 10μF(1) Analog supply voltage Ferrite bead(4) prevents the VDD noise interfering the VDDANA VDDCORE 1.6V to 1.
PAGE 1165
SAM D21 Family Schematic Checklist Figure 42-2. External Analog Reference Schematic With Two References Close to device (for every pin) AREFA EXTERNAL REFERENCE 1 4.7µF 100nF GND AREFB EXTERNAL REFERENCE 2 4.7µF 100nF GND Figure 42-3. External Analog Reference Schematic With One Reference Close to device (for every pin) AREFA EXTERNAL REFERENCE 4.7µF 100nF GND AREFB 100nF GND Table 42-2. External Analog Reference Connections Signal Name Recommended Pin Connection Description AREFx 1.
PAGE 1166
SAM D21 Family Schematic Checklist 42.4 External Reset Circuit The external Reset circuit is connected to the RESET pin when the external Reset function is used. The circuit is not necessary when the RESET pin is not driven LOW externally by the application circuitry. The reset switch can also be removed, if a manual reset is not desired. The RESET pin itself has an internal pull-up resistor, hence it is optional to add any external pull-up resistor. Figure 42-4. External Reset Circuit Schematic VDD 2.
PAGE 1167
SAM D21 Family Schematic Checklist 42.5.1 External Clock Source Figure 42-5. External Clock Source Example Schematic External Clock XIN XOUT/GPIO NC/GPIO Table 42-4. External Clock Source Connections 42.5.2 Signal Name Recommended Pin Connection Description XIN XIN is used as input for an external clock signal Input for inverting oscillator pin XOUT/GPIO Can be left unconnected or used as normal GPIO Crystal Oscillator Figure 42-6.
PAGE 1168
SAM D21 Family Schematic Checklist use a crystal inferior to 12.5pF load capacitance without external capacitors as shown in the following figure. Table 42-6. Maximum ESR Recommendation for 32.768kHz Crystal Crystal CL (pF) Max ESR [kΩ] 12.5 313 Note: Maximum ESR is typical value based on characterization. These values are not covered by test limits in production. Figure 42-7. External Real Time Oscillator without Load Capacitor XIN32 32.
PAGE 1169
SAM D21 Family Schematic Checklist Calculating the Correct Crystal Decoupling Capacitor In order to calculate correct load capacitor for a given crystal, use the model shown in the next figure, which includes internal capacitors CLn, external parasitic capacitance CELn and external load capacitance CPn. CL1 XIN CEL1 CP1 CL2 Internal Figure 42-9. Crystal Circuit With Internal, External and Parasitic Capacitance XOUT External 42.5.
PAGE 1170
SAM D21 Family Schematic Checklist ...........continued 42.6 Symbol Value Description CXOUT32 3.29pF Equivalent internal pin capacitance Unused or Unconnected Pins For unused pins, the default state of the pins for the will provide the lowest current leakage. There is no need to do any configuration of the unused pins in order to lower the power consumption. 42.
PAGE 1171
SAM D21 Family Schematic Checklist 42.7.1 Cortex Debug Connector (10-pin) For debuggers and/or programmers that support the Cortex Debug Connector (10-pin) interface the signals should be connected as shown in the figure below with details described in the next table. Figure 42-11. Cortex Debug Connector (10-pin) VDD Cortex Debug Connector (10-pin) VTref GND 1 SWDIO SWDCLK GND NC NC NC NC nRESET RESET SWCLK SWDIO GND Table 42-10.
PAGE 1172
SAM D21 Family Schematic Checklist Figure 42-12. 10-pin JTAGICE3 Compatible Serial Wire Debug Interface 10-pin JTAGICE3 Compatible VDD Serial Wire Debug Header SWDCLK 1 NC SWDIO GND RESET VTG RESET NC NC NC NC SWCLK SWDIO GND Table 42-11. 10-pin JTAGICE3 Compatible Serial Wire Debug Interface 42.7.
PAGE 1173
SAM D21 Family Schematic Checklist Figure 42-13. 20-pin IDC JTAG Connector VDD 20-pin IDC JTAG Connector VCC NC 1 NC GND NC GND SWDIO GND SWDCLK GND NC GND NC GND* nRESET GND* NC GND* NC GND* RESET SWCLK SWDIO GND Table 42-12. 20-pin IDC JTAG Connector Header Signal Name Description 42.
PAGE 1174
SAM D21 Family Schematic Checklist Table 42-13. USB Interface Checklist Signal Name D+ Recommended Pin Connection • • D- • Description The impedance of the pair should be matched on the PCB to minimize reflections. USB differential tracks should be routed with the same characteristics (length, width, number of vias, etc.
PAGE 1175
SAM D21 Family Conventions 43. 43.1 Conventions Numerical Notation Table 43-1. Numerical Notation 43.2 Symbol Description 165 Decimal number 0b0101 Binary number (example 0b0101 = 5 decimal) '0101' Binary numbers are given without prefix if unambiguous 0x3B24 Hexadecimal number X Represents an unknown or don't care value Z Represents a high-impedance (floating) state for either a signal or a bus Memory Size and Type Table 43-2. Memory Size and Bit Rate 43.
PAGE 1176
SAM D21 Family Conventions ...........continued 43.4 Symbol Description MHz 1 MHz = 106 Hz = 1,000,000 Hz GHz 1 GHz = 109 Hz = 1,000,000,000 Hz s second ms millisecond µs microsecond ns nanosecond Registers and Bits Table 43-4. Register and Bit Mnemonics Symbol Description R/W Read/Write accessible register bit. The user can read from and write to this bit. R Read-only accessible register bit. The user can only read this bit. Writes will be ignored.
PAGE 1177
SAM D21 Family Acronyms and Abbreviations 44. Acronyms and Abbreviations The below table contains acronyms and abbreviations used in this document. Table 44-1.
PAGE 1178
SAM D21 Family Acronyms and Abbreviations ...........
PAGE 1179
SAM D21 Family Acronyms and Abbreviations ...........
PAGE 1180
SAM D21 Family Data Sheet Revision History 45. Data Sheet Revision History Page numbers listed in this section refer to this document. The revision listed in this section refers to the document revision. 45.1 Rev D - 9/2018 Configuration Summary Updated to Add new packages for device variant D. Product Mapping Updated diagram. RTC Updated READREQ register tables. DMAC Updated Channel Control B Register tables. 24.
PAGE 1181
SAM D21 Family Data Sheet Revision History 45.3 Rev. B – 04/2018 General • • 45.4 This revision was updated to include the SAM D21EL and SAM D21GL Variant information, which was released separately in DS40001883A. The SAM D21EL/SAM D21GL Data Sheet (DS40001883A) is superseded by this revision (DS40001882B). IOBUS start addressed is added which was missing in previous revision (DS40001882A).
PAGE 1182
SAM D21 Family Data Sheet Revision History 45.5 Rev. O – 12/2016 General • Introduced Device Variant C. 37. Electrical Characteristics • • Die Revision F characterization is preliminary. 37.7 Power Consumption: Added Standby typical numbers for Device Variant C / Die Revision F. 37.13.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics: Added characterization data for Device Variant C / Die Revision F. • 39.
PAGE 1183
SAM D21 Family Data Sheet Revision History 18. WDT – Watchdog Timer 45.8 • 18.5.7 Debug Operation: Removed the sentence "This peripheral can be forced to continue operation during debugging." The WDT can not be forced to continue operation in debug mode. Rev. L – 09/2016 2. Configuration Summary • Added information on number of pins for the WLCSP pakcage. SAM D21E is offered in 32 pin packages, while the WLCSP has 35 pins. 13. DSU - Device Service Unit • 13.11.
PAGE 1184
SAM D21 Family Data Sheet Revision History 45.9 Rev. K – 09/2016 3. Ordering Information(1) • • SAM D21E: Added Device Variant C ordering codes. Device Identification: Added Device Variant C. 7. I/O Multiplexing and Considerations • The section is reorgnaized: – 7.2.3 SERCOM I2C Pins: Replaces the "Type" column in 7.1 Multiplexed Signals. – 7.2.4 GPIO Clusters: Moved from 37.3 Absolute Maximum Ratings. – 7.2.5 TCC Configurations: Moved from the TCC 31.1 Overview. 16. PM – Power Manager • 16.8.
PAGE 1185
SAM D21 Family Data Sheet Revision History 39. Electrical Characteristics at 125°C • 39.8.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics: Added characterization data for Device Variant C. 39.2 Absolute Maximum Ratings: Updated VPIN minimum and maximum values. (Related to the new Injection Current definition section) • 45.10 Rev. J – 07/2016 3. Ordering Information(1) • SAM D21E: Added ATSAMD21E15B-UUT. 30. TC – Timer/Counter • 30.8.
PAGE 1186
SAM D21 Family Data Sheet Revision History Register Summary: Remove INTENCLR.SYNCRDY. Add MC0 (located in bit 0) for INTENSET and INTFLAG, and left shift MC1, MC2 and MC3 for one bit. Therefore, MC0/1/2/3 are located in bit 0/1/2/3. 37.
PAGE 1187
SAM D21 Family Data Sheet Revision History Register HSOFC.FLENCE description updated. USB Device Registers - Common: Bit description of CTRLB.SPDCONF[1:0] updated. 41. Packaging Information Updated values in 37.2.1 Thermal Resistance Data. Corrected junction temperature equations: TC updated to TJ. Updated package drawing for 41.1.12 35 ball WLCSP (Device Variant B): GPC corrected from GJP to GJR. No other changes. 42. Schematic Checklist Added 42.1.1 Operation in Noisy Environment. Updated section 42.
PAGE 1188
SAM D21 Family Data Sheet Revision History Added pinout figure for 5.4.2 WLCSP35. 9. Product Mapping Updated Internal RWW section to start address from 0x00010000 to 0x00400000. ADC - Analog-to-Digital Converter References to AREFA and AREFB replaced with VREFA and VREFB respectively. 37. Electrical Characteristics Added GPIO cluster note to '37.3 Absolute Maximum Ratings. Added 37.16.5 I2S Timing. Updated BOD33 characteristics. Added characterization data for Device Variant B.
PAGE 1189
SAM D21 Family Data Sheet Revision History Added pinout figures for 5.1.2 UFBGA64 and 5.2.2 WLCSP45. 9. Product Mapping: Updated Product Mapping figure with Internal RWW section block for Device Variant B. 10. Memories: 10.2 Physical Memory Map: Added start address for Internal Read While Write (RWW) section for Device Variant B. 11. Processor And Architecture: 11.1.1 Cortex M0+ Configuration: Removed green connection dots between DMAC Data and AHB-APB Bridge A and Bridge B. 22.
PAGE 1190
SAM D21 Family Data Sheet Revision History 37.11.3 Brown-Out Detectors Characteristics: Added Figure 37-3 and Figure 37-4 and updated conditions in Table 37-21 and Table 37-23. 41. Packaging Information: Added 41.1.4 64-ball UFBGA and 41.1.8 45-ball WLCSP package drawings. 42. Schematic Checklist Updated description in 42.6 Unused or Unconnected Pins. Errata: Device Variant A: - Updated errata for revision A: Added Errata Reference 12291, 13507, 13574.
PAGE 1191
SAM D21 Family Data Sheet Revision History Errata Errata for revision C and E added. 45.18 Rev. B – 07/2014 General: Introduced the new product family name: Atmel | SMART Removed references to Clock Failure Detection. Sub sections within chapters might been moved to other location within the chapter. Typo corrections. 2. Configuration Summary Added 32KB Flash and 4KB SRAM options to SAM D21J and SAM D21G. 3.
PAGE 1192
SAM D21 Family Data Sheet Revision History Added figure Figure 16-2. Register Summary: Removed CFD bit from INTENCLR, INTENSET and INTFLAG. Added PTC bit to APBCMASK register. Register Description: AHB Mask register (AHBMASK): Full bit names updated. APBC Mask register (APBCMASK.PTC): Added PTC to bit 19. CFD bit removed from INTENCLR, INTENSET and INTFLAG. 17. SYSCTRL – System Controller Updated description of 17.6.6 8MHz Internal Oscillator (OSC8M) Operation.
PAGE 1193
SAM D21 Family Data Sheet Revision History Register Summary and Register Description: EVCTRL register: Added bits EXTINTO17 and EXTINTO16 in bit position 17 and 16 respectively. INTENCLR, INTENSET, INTENFLAG registers: Added bits EXTINT17 and EXTINT16 in bit position 17 and 16 respectively. WAKEUP register: Added bits WAKEUPEN17 and WAKEUPEN16 in bit position 17 and 16 respectively. CONFIG2 register added, CONFIG0 and CONFIG1 registers updated: Added bits FILTEN0...31 and SENSE0...31. 22.
PAGE 1194
SAM D21 Family Data Sheet Revision History Introducing Frame Synch Clock. 29.4 Signal Description: Added separate tables for Master-, Slave- and Controller mode. Updated description in 29.5.7 Debug Operation and 29.5.8 Register Access Protection. Updated description in 29.6.1 Principle of Operation. Updated description in sub sections of 29.6.2 Basic Operation. Updated formula in 29.6.2.1.3 MCKn Clock Frequency. Updated formulas in 29.6.2.1.5 Relation Between MCKn, SCKn, and Sampling Frequency fs.
PAGE 1195
SAM D21 Family Data Sheet Revision History Register Description: REFCTRL bit selection names updated from AREFA / AREFB to VREFA / VREFB in Table 33-5 35. DAC – Digital-to-Analog Converter Updated block diagram and signal description: VREFP replaced with VREFB. 37. Electrical Characteristics © 2018 Microchip Technology Inc.
PAGE 1196
SAM D21 Family Data Sheet Revision History Updated VDD max from 3.63V to 3.63V in 37.3 Absolute Maximum Ratings. Updated VDDIN pin from 57 to 56 in 7.2.4 GPIO Clusters. 37.7 Power Consumption: Updated Max values for STANDBY from 190.6μA and 197.3μA to 100μA in Table 37-8. Added 37.8 Peripheral Power Consumption. 37.9 I/O Pin Characteristics: tRISE and tFALL updated with different load conditions depending on the DVRSTR value in . 37.
PAGE 1197
SAM D21 Family Data Sheet Revision History 45.19 Rev. A - 02/2014 Initial released version of this data sheet. © 2018 Microchip Technology Inc.
PAGE 1198
SAM D21 Family The Microchip Web Site Microchip provides online support via our web site at http://www.microchip.com/. This web site is used as a means to make files and information easily available to customers.
PAGE 1199
SAM D21 Family Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PAGE 1200
SAM D21 Family Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
PAGE 1201
SAM D21 Family ISBN: 978-1-5224-3579-2 Quality Management System Certified by DNV ISO/TS 16949 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California ® ® and India. The Company’s quality system processes and procedures are for its PIC MCUs and dsPIC ® DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products.
PAGE 1202
Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.