Datasheet

999
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
38.6.5.4Changing the Synchronous Channels Update Period
It is possible to change the update period of synchronous channels while they are enabled. (See “Method 2:
Manual write of duty-cycle values and automatic trigger of the update” on page 988 and “Method 3: Automatic
write of duty-cycle values and automatic trigger of the update” on page 990.)
To prevent an unexpected update of the synchronous channels registers, the user must use the “PWM Sync
Channels Update Period Update Register” (PWM_SCUPUPD) to change the update period of synchronous
channels while they are still enabled. This register holds the new value until the end of the update period of
synchronous channels (when UPRCNT is equal to UPR in “PWM Sync Channels Update Period Register”
(PWM_SCUP)) and the end of the current PWM period, then updates the value for the next period.
Note: If the update register PWM_SCUPUPD is written several times between two updates, only the last written value is
taken into account.
Note: Changing the update period does make sense only if there is one or more synchronous channels and if the update
method 1 or 2 is selected (UPDM = 1 or 2 in “PWM Sync Channels Mode Register” ).
Figure 38-18. Synchronized Update of Update Period Value of Synchronous Channels
End of PWM period and
end of Update Period
of Synchronous Channels
PWM_SCUPUPD Value
User's
Writing
PWM_SCUP