Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
986
Table 38-5. Summary of the Update of Registers of Synchronous Channels
UPDM=0 UPDM=1 UPDM=2
Period Value
(
PWM_CPRDUPDx)
Write by the CPU
Update is triggered at the
next PWM period as soon as
the bit UPDULOCK is set to 1
Dead-Time Values
(
PWM_DTUPDx)
Write by the CPU
Update is triggered at the
next PWM period as soon as
the bit UPDULOCK is set to 1
Duty-Cycle Values
(
PWM_CDTYUPDx)
Write by the CPU Write by the CPU Write by the PDC
Update is triggered at the next
PWM period as soon as the bit
UPDULOCK is set to 1
Update is triggered at the next
PWM period as soon as the update period
counter has reached the value UPR
Update Period Value
(
PWM_SCUPUPD)
Not applicable Write by the CPU
Not applicable
Update is triggered at the next
PWM period as soon as the update period
counter has reached the value UPR