Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
984
The fault protection on a channel is triggered when this channel is enabled and when any one of the faults that are
enabled for this channel is active. It can be triggered even if the PWM master clock (MCK) is not running but only
by a fault input that is not glitch filtered.
When the fault protection is triggered on a channel, the fault protection mechanism forces the channel outputs to
the values defined by the fields FPVHx and FPVLx in the “PWM Fault Protection Value Register” (PWM_FPV) and
leads to a reset of the counter of this channel. The output forcing is made asynchronously to the channel counter.
CAUTION:
 To prevent an unexpected activation of the status flag FSy in the PWM_FSR register, the FMODy bit can be
set to “1” only if the FPOLy bit has been previously configured to its final value.
 To prevent an unexpected activation of the Fault Protection on the channel x, the bit FPEx[y] can be set to
“1” only if the FPOLy bit has been previously configured to its final value.
If a comparison unit is enabled (see Section 38.6.3 “PWM Comparison Units”) and if a fault is triggered in the
channel 0, in this case the comparison cannot match.
As soon as the fault protection is triggered on a channel, an interrupt (different from the interrupt generated at the
end of the PWM period) can be generated but only if it is enabled and not masked. The interrupt is reset by reading
the interrupt status register, even if the fault which has caused the trigger of the fault protection is kept active.