Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
978
38.6.2.2 Comparator
The comparator continuously compares its counter value with the channel period defined by CPRD in the “PWM
Channel Period Register” on page 1048 (PWM_CPRDx) and the duty-cycle defined by CDTY in the “PWM
Channel Duty Cycle Register” on page 1046 (PWM_CDTYx) to generate an output signal OCx accordingly.
The different properties of the waveform of the output OCx are:
 the clock selection. The channel counter is clocked by one of the clocks provided by the clock generator
described in the previous section. This channel parameter is defined in the CPRE field of the “PWM Channel
Mode Register” on page 1044 (PWM_CMRx). This field is reset at 0.
 the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register.
If the waveform is left aligned, then the output waveform period depends on the counter source clock and
can be calculated:
By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
64, 128, 256, 512, or 1024), the resulting period formula will be:
By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
If the waveform is center aligned then the output waveform period depends on the counter source clock and
can be calculated:
By using the PWM master clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
 the waveform duty-cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx
register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
 the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is
defined in the CPOL field of the PWM_CMRx register. By default the signal starts by a low level.
XCPRD×()
MCK
-------------------------------
CRPD DIVA×()
MCK
------------------------------------------
CRPD DIVB×()
MCK
------------------------------------------
2 XCPRD××()
MCK
----------------------------------------
2 CPRD DIVA××()
MCK
---------------------------------------------------
2 CPRD× DIVB×()
MCK
---------------------------------------------------
duty cycle
period 1 fchannel_x_clock CDTY×⁄–()
period
----------------------------------------------------------------------------------------------------
=
duty cycle
period 2⁄()1 fchannel_x_clock CDTY×⁄–())
period 2⁄()
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=