Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
934
–SRC_WIDTH is set to BYTE.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer).
o. Program LLI_B(n).DMAC_CTRLBx with the following field’s values:
 DST_INCR is set to INCR.
 SRC_INCR is set to INCR.
 FC field is programmed with peripheral to memory flow control mode.
 Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or Next descriptor
location points to 0.
 DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is
able to prefetch data and write HSMCI simultaneously.
p. Progra m LLI_B(n).DMAC_CFGx memory location for channel x with the following field’s values:
 FIFOCFG defines the watermark of the DMAC channel FIFO.
 SRC_H2SEL is set to true to enable hardware handshaking on the destination.
 SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller
q. Program LLI_B(n).DMAC_DSCR with addr
ess of des
criptor LLI_W(n+1). If LLI_B(n) is the last
descriptor, then program LLI_B(n).DMAC_DSCR with 0.
r. Program DMAC_CTRLBx register for channel x with 0, its content is u pdated with the LLI Fetch
operation.
s.Program DMAC_DSCRx with the address of LLI_W(0) if block_length is greater than 4 else with
address of LLI_B(0).
t. Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request.
4. Enable DMADONE interrupt in the HSMCI_IER register.
5. Poll CBTC[x] bit in the DMAC_EBCISR Register.
6. If a new list of buffers shall be transferred, repeat step 7. Check and handle HSMCI errors.
7. Poll FIFOEMPTY field in the HSMCI_SR.
8. Send The STOP_TRANSMISSION command writing HSMCI_ARG then HSMCI_CMDR.
9. Wait for XFRDONE in HSMCI_SR register.