Datasheet

931
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
37.8.8 READ_MULTIPLE_BLOCK
37.8.8.1 Block Length is a Multiple of 4
1. Wait until the current command execution has successfully terminated.
a.Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR.
2. Program the block length in the card. This value defines the value block_length.
3. Program the block length in the HSMCI configuration register with block_length value.
4. Set RDPROOF bit in HSMCI_MR to avoid overflow.
5. Program HSMCI_DMA register with the following fields:
 ROPT field is set to 0.
 OFFSET field is set to 0.
 CHKSIZE is user defined.
 DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit was previously
set to false.
6. Issue a READ_MULTIPLE_BLOCK command.
7. Program the DMA Controller to use a list of descriptors:
a.Read the channel Register to choose an available (disabled) channel.
b.Clear any pending interrupts on the channel from the previous DMA transfer by reading the
DMAC_EBCISR registe
r.
c.
Program the channel registers in the Memory with the first descriptor. This descriptor will be word ori-
ented. This descriptor is referred to as LLI_W(n), standing for LLI word oriented tra nsfer for block n.
d. The LLI_W(n).DMAC_SADDRx field in memory must be set with the starting address of the
HSMCI_FIFO address.
e. The LLI_W(n).DMAC_DADDRx field in the memory must be word aligned.
f. Program LLI_W(n).DMAC_CTRLAx with the following field’s values:
–DST_WIDTH is set to WORD
–SRC_WIDTH is set to WORD
–SCSIZ
E must be s
et according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length/4.
g. Program LLI_W(n).DMAC_CTRLBx with the following field’s values:
–DST_INCR is set to INCR.
–SRC_INCR is set to INCR.
–FC field is programmed with peripheral to memory flow control mode.
–SRC_DSCR is set to 0 (descriptor fetch is enabled for the SRC).
–DST_DSCR is set to TRUE (descriptor fetch is disabled for the DST).
–DIF and SIF are set with their respe
ct
ive layer ID. If SIF is different from DIF, the DMA Controller is
able to prefetch data and write HSMCI simultaneously.
h. Program LLI_W(n).DMAC_CFGx register for channel x with the following field’s values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–DST_REP is set to zero. Addresses are contiguous.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is program
med with the hard
ware handshaking ID of the targeted HSMCI Host
Controller.