Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
82
CLZ Rd, Rm Count leading zeros - page 116
CMN, CMNS Rn, Op2 Compare Negative N,Z,C,V page 117
CMP, CMPS Rn, Op2 Compare N,Z,C,V page 117
CPSID iflags Change Processor State, Disable Interrupts - page 143
CPSIE iflags Change Processor State, Enable Interrupts - page 143
DMB - Data Memory Barrier - page 144
DSB - Data Synchronization Barrier - page 144
EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C page 113
ISB - Instruction Synchronization Barrier - page 145
IT - If-Then condition block - page 137
LDM Rn{!}, reglist Load Multiple registers, increment after - page 103
LDMDB, LDMEA Rn{!}, reglist Load Multiple registers, decrement before - page 103
LDMFD, LDMIA Rn{!}, reglist Load Multiple registers, increment after - page 103
LDR Rt, [Rn, #offset] Load Register with word - page 98
LDRB, LDRBT Rt, [Rn, #offset] Load Register with byte - page 98
LDRD Rt, Rt2, [Rn, #offset] Load Register with two bytes - page 98
LDREX Rt, [Rn, #offset] Load Register Exclusive - page 98
LDREXB Rt, [Rn] Load Register Exclusive with byte - page 98
LDREXH Rt, [Rn] Load Register Exclusive with halfword - page 98
LDRH, LDRHT Rt, [Rn, #offset] Load Register with halfword - page 98
LDRSB, LDRSBT Rt, [Rn, #offset] Load Register with signed byte - page 98
LDRSH, LDRSHT Rt, [Rn, #offset] Load Register with signed halfword - page 98
LDRT Rt, [Rn, #offset] Load Register with word - page 98
LSL, LSLS Rd, Rm, <Rs|#n> Logical Shift Left N,Z,C page 114
LSR, LSRS Rd, Rm, <Rs|#n> Logical Shift Right N,Z,C page 114
MLA Rd, Rn, Rm, Ra Multiply with Accumulate, 32-bit result - page 124
MLS Rd, Rn, Rm, Ra Multiply and Subtract, 32-bit result - page 124
MOV, MOVS Rd, Op2 Move N,Z,C page 118
MOVT Rd, #imm16 Move Top - page 120
MOVW, MOV Rd, #imm16 Move 16-bit constant N,Z,C page 118
MRS Rd, spec_reg Move from special register to general register - page 146
MSR spec_reg, Rm Move from general register to special register N,Z,C,V page 147
MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z page 124
MVN, MVNS Rd, Op2 Move NOT N,Z,C page 118
NOP - No Operation - page 148
ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C page 113
ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C page 113
Table 10-13. Cortex-M3 instructions (Continued)
Mnemonic Operands Brief description Flags Page