Datasheet

807
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
As soon as the Synch Break Field is transmitted, the flag LINBK in the Channel Status register (US_CSR) is set to
1. Likewise, as soon as the Identifier Field is sent, the flag LINID in the Channel Status register (US_CSR) is set to
1. These flags are reset by writing the bit RSTSTA to 1 in the Control register (US_CR).
Figure 35-40. Header Transmission
TXD
Baud Rate
Clock
Start
Bit
Write
US_LINIR
10101010
TXRDY
Stop
Bit
Start
Bit
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7Break Field
13 dominant bits (at 0)
Stop
Bit
Break
Delimiter
1 recessive bit
(at 1)
Synch Byte = 0x55
US_LINIR
ID
LINID
in US_CSR
LINBK
in US_CSR
Write RSTSTA=1
in US_CR