Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
78
10.7 Fault handling
Faults are a subset of the exceptions, see “Exception model” on page 70. The following generate a fault:
 a bus error on:
 an instruction fetch or vector table load
 a data access
 an internally-detected error such as an undefined instruction or an attempt to change state with a BX
instruction
 attempting to execute an instruction from a memory region marked as Non-Executable (XN).
 an MPU fault because of a privilege violation or an attempt to access an unmanaged region.
10.7.1 Fault types
Table 10-11 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the
register bit that indicates that the fault has occurred. See “Configurable Fault Status Register” on page 182 for
more information about the fault status registers.
Table 10-11. Faults
Fault Handler Bit name Fault status register
Bus error on a vector read
Hard fault
VECTTBL
“Hard Fault Status Register” on page 188
Fault escalated to a hard fault FORCED
MPU mismatch:
Memory
management
fault
--
on instruction access IACCVIOL
(1)
1. Occurs on an access to an XN region even if the MPU is disabled.
“Memory Management Fault Address
Register” on page 189
on data access DACCVIOL
during exception stacking MSTKERR
during exception unstacking MUNSKERR
Bus error:
Bus fault
--
during exception stacking STKERR
“Bus Fault Status Register” on page 184
during exception unstacking UNSTKERR
during instruction prefetch IBUSERR
Precise data bus error PRECISERR
Imprecise data bus error IMPRECISERR
Attempt to access a coprocessor
Usage fault
NOCP
“Usage Fault Status Register” on page 186
Undefined instruction UNDEFINSTR
Attempt to enter an invalid instruction
set state
(2)
2. Attempting to use an instruction set other than the Thumb instruction set.
INVSTATE
Invalid EXC_RETURN value INVPC
Illegal unaligned load or store UNALIGNED
Divide By 0 DIVBYZERO