Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
76
exception. State saving is not affected by late arrival because the state saved is the same for both exceptions.
Therefore the state saving continues uninterrupted. The processor can accept a late arriving exception until the
first instruction of the exception handler of the original exception enters the execute stage of the processor. On
return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply.
10.6.7.5 Exception entry
Exception entry occurs when there is a pending exception with sufficient priority and either:
 the processor is in Thread mode
 the new exception is of higher priority than the exception being handled, in which case the new exception
preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask registers, see “Exception
mask registers” on page 56. An exception with less priority than this is pending but is not handled by the
processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the
processor pushes information onto the current stack. This operation is referred as stacking and the structure of
eight data words is referred as stack frame. The stack frame contains the following information:
 R0-R3, R12
 Return address
 PSR
 LR.
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. Unless stack
alignment is disabled, the stack frame is aligned to a double-word address. If the STKALIGN bit of the
Configuration Control Register (CCR) is set to 1, stack align adjustment is performed during stacking.
The stack frame includes the return address. This is the address of the next instruction in the interrupted program.
This value is restored to the PC at exception return so that the interrupted program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start
address from the vector table. When stacking is complete, the processor starts executing the exception handler. At
the same time, the processor writes an EXC_RETURN value to the LR. This indicates which stack pointer
corresponds to the stack frame and what operation mode the was processor was in before the entry occurred.
If no higher priority exception occurs during exception entry, the processor starts executing the exception handler
and automatically changes the status of the corresponding pending interrupt to active.
If another higher priority exception occurs during exception entry, the processor starts executing the exception
handler for this exception and does not change the pending status of the earlier exception. This is the late arrival
case.
10.6.7.6 Exception return
Exception return occurs when the processor is in Handler mode and executes one of the following instructions to
load the EXC_RETURN value into the PC:
 a POP instruction that includes the PC
 a BX instruction with any register.
 an LDR or LDM instruction with the PC as the destination.
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value
to detect when the processor has completed an exception handler. The lowest four bits of this value provide
information on the return stack and processor mode. Table 10-10 shows the EXC_RETURN[3:0] values with a
description of the exception return behavior.