Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
756
Figure 34-10. Transmitter Control
34.5.4 Peripheral DMA Controller
Both the receiver and the transmitter of the UART are connected to a Peripheral DMA Controller (PDC) channel.
The peripheral data controller channels are programmed via registers that are mapped within the UART user
interface from the offset 0x100. The status bits are reported in the UART status register (UART_SR) and can
generate an interrupt.
The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in
UART_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of
data in UART_THR.
UART_THR
Shift Register
UTXD
TXRDY
TXEMPTY
Data 0Data 1
Data 0
Data 0
Data 1
Data 1S
S PP
Write Data 0
in UART_THR
Write Data 1
in UART_THR
stop
stop