Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
732
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
SADR.
3. SCLWS is automatically set when the clock synchronization mechanism is started.
Clock Synchronization in Write Mode
The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was
not detected, it is tied low until TWI_RHR is read.
Figure 33-29 on page 732 describes the clock synchronization in Read mode.
Figure 33-29. Clock Synchronization in Write Mode
Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
SADR.
2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the
mechanism is finished.
33.10.5.5Reversal after a Repeated Start
Reversal of Read to Write
The master initiates the communication by a read command and finishes it by a write command.
Figure 33-30 on page 733 describes the repeated start + reversal from Read to Write mode.
Rd DATA0
Rd DATA1
Rd DATA2
SVACC
SVREAD
RXRDY
SCLWS
TXCOMP
DATA 1
DATA 2
SCL is stretched on the last bit of DATA1
As soon as a START is detected
TWCK
TWD
TWI_RHR
CLOCK is tied low by the TWI as long as RHR is full
DATA0 is not read in the RHR
ADRSSADR W ADATA 0A A DATA 2DATA 1 S
NA