Datasheet

731
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
In case of a WRITE command, the programmer has to decode the programming sequence and program a new
SADR if the programming sequence matches.
Figure 33-27 on page 731 describes the General Call access.
Figure 33-27. Master Performs a General Call
Note: This method allows the user to create an own programming sequence by choosing the programming bytes and the
number of them. The programming sequence has to be provided to the master.
33.10.5.4Clock Synchronization
In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the
emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching
mechanism is implemented.
Clock Synchronization in Read Mode
The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected.
It is tied low until the shift register is loaded.
Figure 33-28 on page 731 describes the clock synchronization in Read mode.
Figure 33-28. Clock Synchronization in Read Mode
Notes: 1. TXRDY is reset when data has been written in the TWI_THR to the shift register and set when this data has been
acknowledged or non acknowledged.
0000000 + W
GENERAL CALL
P
S
A
GENERAL CALL Reset or write DADD
A New SADR
DATA 1
A DATA 2
A
A
New SADR
Programming sequence
TXD
GCACC
SVACC
RESET command = 00000110X
WRITE command = 00000100X
Reset after read
DATA 1
The clock is stretched after the ACK, the state of TWD is undefined during clock stretching
SCLWS
SVACC
SVREAD
TXRDY
TWCK
TWI_THR
TXCOMP
The data is memorized in TWI_THR until a new value is written
TWI_THR is transmitted to the shift register
Ack or Nack from the master
DATA 0DATA 0 DATA 2
1
2
1
CLOCK is tied low by the TWI
as long as THR is empty
S
SADR
S
R DATA0A
A
DATA 1
A DATA 2 NA S
XXXXXXX
2
Write THR
As soon as a START is detected