Datasheet

73
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
Privileged software can disable the exceptions that Table 10-9 on page 72 shows as having configurable priority,
see:
 “System Handler Control and State Register” on page 180
 “Interrupt Clear-enable Registers” on page 156.
For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault
handling” on page 78.
10.6.3 Exception handlers
The processor handles exceptions using:
10.6.3.1 Interrupt Service Routines (ISRs)
Interrupts IRQ0 to IRQ29 are the exceptions handled by ISRs.
10.6.3.2 Fault handlers
Hard fault, memory management fault, usage fault, bus fault are fault exceptions handled by the fault handlers.
10.6.3.3 System handlers
NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions that are handled by system
handlers.
10.6.4 Vector table
The vector table contains the reset value of the stack pointer, and the start addresses, also called exception
vectors, for all exception handlers. Figure 10-3 on page 74 shows the order of the exception vectors in the vector
table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code.