Datasheet

729
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
See Figure 33-25 on page 730.
33.10.4.2Write Sequence
In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as
soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when
reading the TWI_RHR.
TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR
is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset.
See Figure 33-26 on page 730.
33.10.4.3Clock Synchronization Sequence
In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock synchronization.
Clock stretching information is given by the SCLWS (Clock Wait state) bit.
See Figure 33-28 on page 731 and Figure 33-29 on page 732.
33.10.4.4General Call
In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set.
After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the
new address programming sequence.
See Figure 33-27 on page 731.
33.10.4.5PDC
As it is impossible to know the exact number of data to receive/send, the use of PDC is NOT recommended in
SLAVE mode.
33.10.5 Data Transfer
33.10.5.1Read Operation
The read mode is defined as a data requirement from the master.
After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave
address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer.
Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR
register.
If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
Figure 33-25 on page 730 describes the write operation.