Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
718
33.8.7 Using the Peripheral DMA Controller (PDC)
The use of the PDC significantly reduces the CPU load.
To assure correct implementation, respect the following programming sequences:
33.8.7.1 Data Transmit with the PDC
1. Initialize the transmit PDC (memory pointers, size, etc.).
2. Configure the master mode (DADR, CKDIV, etc.).
3. Start the transfer by setting the PDC TXTEN bit.
4. Wait for the PDC end TX flag.
5. Disable the PDC by setting the PDC TXDIS bit.
33.8.7.2 Data Receive with the PDC
1. Initialize the receive PDC (memory pointers, size - 1, etc.).
2. Configure the master mode (DADR, CKDIV, etc.).
3. Start the transfer by setting the PDC RXTEN bit.
4. Wait for the PDC end RX flag.
5. Disable the PDC by setting the PDC RXDIS bit.
33.8.8 SMBUS Quick Command (Master Mode Only)
The TWI interface can perform a Quick Command:
1. Configure the master mode (DADR, CKDIV, etc.).
2. Write the MREAD bit in the TWI_MMR register at the value of the one-bit command to be sent.
3. Start the transfer by setting the QUICK bit in the TWI_CR.
Figure 33-14. SMBUS Quick Command
33.8.9 Read-write Flowcharts
The following flowcharts shown in Figure 33-16 on page 720, Figure 33-17 on page 721, Figure 33-18 on page
722, Figure 33-19 on page 723 and Figure 33-20 on page 724 give examples for read and write operations. A
polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt
enable register (TWI_IER) be configured first.
TXCOMP
TXRDY
Write QUICK command in TWI_CR
TWD
AS DADR R/W P