Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
66
10.5.4.2 DSB
The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete
before subsequent instructions execute. See “DSB” on page 144.
10.5.4.3 ISB
The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory transactions is
recognizable by subsequent instructions. See “ISB” on page 145.
Use memory barrier instructions in, for example:
 MPU programming:
 Use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of context
switching.
 Use an ISB instruction to ensure the new MPU setting takes effect immediately after programming the
MPU region or regions, if the MPU configuration code was accessed using a branch or call. If the MPU
configuration code is entered using exception mechanisms, then an ISB instruction is not required.
 Vector table. If the program changes an entry in the vector table, and then enables the corresponding
exception, use a DMB instruction between the operations. This ensures that if the exception is taken
immediately after being enabled the processor uses the new exception vector.
 Self-modifying code. If a program contains self-modifying code, use an ISB instruction immediately after the
code modification in the program. This ensures subsequent instruction execution uses the updated program.
 Memory map switching. If the system contains a memory map switching mechanism, use a DSB instruction
after switching the memory map in the program. This ensures subsequent instruction execution uses the
updated memory map.
 Dynamic exception priority change. When an exception priority has to change when the exception is pending
or active, use DSB instructions after the change. This ensures the change takes effect on completion of the
DSB instruction.
 Using a semaphore in multi-master system. If the system contains more than one bus master, for example, if
another processor is present in the system, each processor must use a DMB instruction after any
semaphore instructions, to ensure other bus masters see the memory transactions in the order in which they
were executed.
Memory accesses to Strongly-ordered memory, such as the system control block, do not require the use of DMB
instructions.
10.5.5 Bit-banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band
regions occupy the lowest 1MB of the SRAM and peripheral memory regions.
The memory map has two 32MB alias regions that map to two 1MB bit-band regions:
 accesses to the 32MB SRAM alias region map to the 1MB SRAM bit-band region, as shown in Table 10-6
 accesses to the 32MB peripheral alias region map to the 1MB peripheral bit-band region, as shown in Table
10-7.