Datasheet
65
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
10.5.3.1 Additional memory access constraints for shared memory
When a system includes shared memory, some memory regions have additional access constraints, and some
regions are subdivided, as Table 10-5 shows:
10.5.4 Software ordering of memory accesses
The order of instructions in the program flow does not always guarantee the order of the corresponding memory
transactions. This is because:
the processor can reorder some memory accesses to improve efficiency, providing this does not affect the
behavior of the instruction sequence.
the processor has multiple bus interfaces
memory or devices in the memory map have different wait states
some memory accesses are buffered or speculative.
“Memory system ordering of memory accesses” on page 63 describes the cases where the memory system
guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, software must
include memory barrier instructions to force that ordering. The processor provides the following memory barrier
instructions:
10.5.4.1
DMB
The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before
subsequent memory transactions. See “DMB” on page 144.
Table 10-5. Memory region share ability policies
Address range Memory region Memory type Shareability
0x00000000
-
0x1FFFFFFF
Code Normal
(1)
1. See “Memory regions, types and attributes” on page 62 for more information.
-
0x20000000
-
0x3FFFFFFF
SRAM Normal
(1)
-
0x40000000
-
0x5FFFFFFF
Peripheral
(2)
2. The Peripheral and Vendor-specific device regions have no additional access constraints.
Device
(1)
-
0x60000000
-
0x7FFFFFFF
External RAM Normal
(1)
-
WBWA
(2)
0x80000000
-
0x9FFFFFFF
WT
(2)
0xA0000000
-
0xBFFFFFFF
External device Device
(1)
Shareable
(1)
-
0xC0000000
-
0xDFFFFFFF
Non-
shareable
(1)
0xE0000000
-
0xE00FFFFF
Private Peripheral
Bus
Strongly-
ordered
(1)
Shareable
(1)
-
0xE0100000
-
0xFFFFFFFF
Vendor-specific
device
(2)
Device
(1)
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