Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
626
These Additional Modes are:
 Rising Edge Detection
 Falling Edge Detection
 Low Level Detection
 High Level Detection
In order to select an Additional Interrupt Mode:
 The type of event detection (Edge or Level) must be selected by writing in the set of registers; PIO_ESR
(Edge Select Register) and PIO_LSR (Level Select Register) which enable respectively, the Edge and Level
Detection. The current status of this selection is accessible through the PIO_ELSR (Edge/Level Status
Register).
 The Polarity of the event detection (Rising/Falling Edge or High/Low Level) must be selected by writing in
the set of registers; PIO_FELLSR (Falling Edge /Low Level Select Register) and PIO_REHLSR (Rising
Edge/High Level Select Register) which allow to select Falling or Rising Edge (if Edge is selected in the
PIO_ELSR) Edge or High or Low Level Detection (if Level is selected in the PIO_ELSR). The current status
of this selection is accessible through the PIO_FRLHSR (Fall/Rise - Low/High Status Register).
When an input Edge or Level is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status
Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The
interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the
Nested Vector Interrupt Controller (NVIC).
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts
that are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a “Level”, the interrupt
is generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed.