Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
622
31.5.1 Pull-up Resistor Control
Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by
writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in
these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading
a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled.
Control of the pull-up resistor is possible regardless of the configuration of the I/O line.
After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0.
31.5.2 I/O Line or Peripheral Function Selection
When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers
PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status
Register) is the result of the set and clear registers and indicates whether the pin is controlled by the
corresponding peripheral or by the PIO Controller. A value of 0 indicates that the pin is controlled by the
corresponding on-chip peripheral selected in the PIO_ABSR (AB Select Register). A value of 1 indicates the pin is
controlled by the PIO controller.
If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR
have no effect and PIO_PSR returns 1 for the corresponding bit.
After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in
some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select
lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an
external memory). Thus, the reset value of PIO_PSR is defined at the product level, depending on the multiplexing
of the device.
31.5.3 Peripheral A or B Selection
The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The selection is
performed by writing PIO_ABSR (AB Select Register). For each pin, the corresponding bit at level 0 means
peripheral A is selected whereas the corresponding bit at level 1 indicates that peripheral B is selected.
Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral input lines are always
connected to the pin input.
After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A. However,
peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode.
Writing in PIO_ABSR manages the multiplexing regardless of the configuration of the pin. However, assignment of
a pin to a peripheral function requires a write in the peripheral selection register (PIO_ABSR) in addition to a write
in PIO_PDR.