Datasheet

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SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
10.4.4 Exceptions and interrupts
The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored
Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software
control. The processor uses handler mode to handle all exceptions except for reset. See “Exception entry” on page
76 and “Exception return” on page 76 for more information.
The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller” on page 152 for more
information.
10.4.5 Data types
The processor:
 supports the following data types:
 32-bit words
 16-bit halfwords
 8-bit bytes
 supports 64-bit data transfer instructions.
 manages all data memory accesses as little-endian. Instruction memory and Private Peripheral Bus (PPB)
accesses are always little-endian. See “Memory regions, types and attributes” on page 62 for more
information.
10.4.6 The Cortex Microcontroller Software Interface Standard
For a Cortex-M3 microcontroller system, the Cortex Microcontroller Software Interface Standard (CMSIS) defines:
 a common way to:
 access peripheral registers
 define exception vectors
 the names of:
 the registers of the core peripherals
 the core exception vectors
 a device-independent interface for RTOS kernels, including a debug channel.
The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M3 processor. It
also includes optional interfaces for middleware components comprising a TCP/IP stack and a Flash file system.
CMSIS simplifies software development by enabling the reuse of template code and the combination of CMSIS-
compliant software components from various middleware vendors. Software vendors can expand the CMSIS to
include their peripheral definitions and access functions for those peripherals.
This document includes the register names defined by the CMSIS, and gives short descriptions of the CMSIS
functions that address the processor core and the core peripherals.
This document uses the register short names defined by the CMSIS. In a few cases these differ from the
architectural short names that might be used in other documents.
The following sections give more information about the CMSIS:
 “Power management programming hints” on page 81
 “Intrinsic functions” on page 85
 “The CMSIS mapping of the Cortex-M3 NVIC registers” on page 153
 “NVIC programming hints” on page 164.