Datasheet

595
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
• CKG: Receive Clock Gating Selection
• START: Receive Start Selection
• STOP: Receive Stop Selection
0 = After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a
new compare 0.
1 = After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
• STTDLY: Receive Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception.
When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied.
Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG
(Receive Sync Data) reception.
• PERIOD: Receive Period Divider Selection
This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no
PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.
Value Name Description RK Pin
0 NONE None Input-only
1 CONTINUOUS Continuous Receive Clock Output
2 TRANSFER
Receive Clock only during data transfers Output
3-7
Reserved
Value Name Description
0CONTINUOUS
Continuous, as soon as the receiver is enabled, and
immediately after the end of transfer of the previous data.
1 TRANSMIT Transmit start
2RF_LOW
Detection of a low level on RF signal
3 RF_HIGH
Detection of a high level on RF signal
4RF_FALLING
Detection of a falling edge on RF signal
5 RF_RISING
Detection of a rising edge on RF signal
6 RF_LEVEL
Detection of any level change on RF signal
7RF_EDGE
Detection of any edge on RF signal
8CMP_0
Compare 0