Datasheet

55
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
7-10 = Reserved
11 = SVCall
12 = Reserved for Debug
13 = Reserved
14 = PendSV
15 = SysTick
16 = IRQ0
45 = IRQ29
see “Exception types” on page 71 for more information.
10.4.3.8 Execution Program Status Register
The EPSR contains the Thumb state bit, and the execution state bits for either the:
 If-Then (IT) instruction
 Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction.
See the register summary in Table 10-2 on page 51 for the EPSR attributes. The bit assignments are:
•ICI
Interruptible-continuable instruction bits, see “Interruptible-continuable instructions” on page 55.
•IT
Indicates the execution state bits of the
IT instruction, see “IT” on page 137.
•T
Always set to 1.
Attempts to read the EPSR directly through application software using the MSR instruction always return zero.
Attempts to write the EPSR using the MSR instruction in application software are ignored. Fault handlers can
examine EPSR value in the stacked PSR to indicate the operation that is at fault. See “Exception entry and return”
on page 75.
10.4.3.9 Interruptible-continuable instructions
When an interrupt occurs during the execution of an LDM or STM instruction, the processor:
 stops the load multiple or store multiple instruction operation temporarily
 stores the next register operand in the multiple operation to EPSR bits[15:12].
After servicing the interrupt, the processor:
 returns to the register pointed to by bits[15:12]
 resumes execution of the multiple load or store instruction.
When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.
10.4.3.10 If-Then block
The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in the block is
conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See
“IT” on page 137 for more information.