Datasheet

545
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
28.15.7 PMC UTMI Clock Configuration Register
Name: CKGR_UCKR
Address: 0x400E061C
Access: Read-write
This register can only be written if the WPEN bit is cleared in the “PMC Write Protect Mode Register” .
• UPLLEN: UTMI PLL Enable
0: The UTMI PLL is disabled.
1: The UTMI PLL is enabled.
When UPLLEN is set, the LOCKU flag is set once the UTMI PLL startup time is achieved.
• UPLLCOUNT: UTMI PLL Start-up Time
Specifies the number of Slow Clock cycles multiplied by 8 for the UTMI PLL start-up time.
31 30 29 28 27 26 25 24
––– ––––
23 22 21 20 19 18 17 16
UPLLCOUNT – – – UPLLEN
15 14 13 12 11 10 9 8
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