Datasheet

537
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
28.14 Write Protection Registers
To prevent any single software error that may corrupt PMC behavior, certain address spaces can be write
protected by setting the WPEN bit in the “PMC Write Protect Mode Register” (PMC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the PMC Write Protect Status
Register (PMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been
attempted.
The WPVS flag is reset by writing the PMC Write Protect Mode Register (PMC_WPMR) with the appropriate
access key, WPKEY.
The protected registers are:
“PMC System Clock Enable Register”
“PMC System Clock Disable Register”
“PMC Peripheral Clock Enable Register 0”
“PMC Peripheral Clock Disable Register 0”
“PMC Clock Generator Main Oscillator Register”
“PMC Clock Generator PLLA Register”
“PMC UTMI Clock Configuration Register”
“PMC Master Clock Register”
“PMC USB Clock Register”
“PMC Programmable Clock Register”
“PMC Fast Startup Mode Register”
“PMC Fast Startup Polarity Register”
“PMC Peripheral Clock Enable Register 1”
“PMC Peripheral Clock Disable Register 1”