Datasheet

525
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the
number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field.
The PLL clock can be divided by 2 by writing the PLLDIV2 (PLLADIV2) bit in PMC Master Clock Register
(PMC_MCKR).
It is forbidden to change 4/8/12 MHz Fast RC oscillator, or main selection in CKGR_MOR register while Master
clock source is PLL and PLL reference clock is the Fast RC oscillator.
The user must:
 Switch on the Main RC oscillator by writing 1 in CSS field of PMC_MCKR.
 Change the frequency (MOSCRCF) or oscillator selection (MOSCSEL) in CKGR_MOR.
 Wait for MOSCRCS (if frequency changes) or MOSCSELS (if oscillator selection changes) in PMC_IER.
 Disable and then enable the PLL (LOCK in PMC_IDR and PMC_IER).
 Wait for PLLRDY.
 Switch back to PLL.
27.7 UTMI Phase Lock Loop Programming
The source clock of the UTMI PLL is the 3-20 MHz crystal oscillator. A 12 MHz crystal is needed to use the USB.
Figure 27-5. UTMI PLL Block Diagram
Whenever the UTMI PLL is enabled by writing UPLLEN in CKGR_UCKR, the LOCKU bit in PMC_SR is
automatically cleared. The values written in the PLLCOUNT field in CKGR_UCKR are loaded in the UTMI PLL
counter. The UTMI PLL counter then decrements at the speed of the Slow Clock divided by 8 until it reaches 0. At
this time, the LOCKU bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the
number of Slow Clock cycles required to cover the UTMI PLL transient time into the PLLCOUNT field.
UTMI PLL
UPLLEN
UPLLCOUNT
LOCKU
SLCK
MAINCK
UPLLCK
UTMI PLL
Counter