Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
524
27.5.4 Main Clock Frequency Counter
The device features a Main Clock frequency counter that provides the frequency of the Main Clock.
The Main Clock frequency counter is reset and starts incrementing at the Main Clock speed after the next rising
edge of the Slow Clock in the following cases:
 when the 4/8/12 MHz Fast RC oscillator clock is selected as the source of Main Clock and when this
oscillator becomes stable (i.e., when the MOSCRCS bit is set)
 when the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator is selected as the source of Main Clock
and when this oscillator becomes stable (i.e., when the MOSCXTS bit is set)
 when the Main Clock Oscillator selection is modified
Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the Clock Generator Main Clock Frequency
Register (CKGR_MCFR) is set and the counter stops counting. Its value can be read in the MAINF field of
CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of Slow Clock, so that the frequency
of the 4/8/12 MHz Fast RC oscillator or 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator can be
determined.
27.6 Divider and PLL Block
The device features one Divider/PLL Block that permits a wide range of frequencies to be selected on either the
master clock, the processor clock or the programmable clock outputs. Additionally, they provide a 48 MHz signal to
the embedded USB device port regardless of the frequency of the main clock.
Figure 27-4 shows the block diagram of the dividers and PLL blocks.
Figure 27-4. Dividers and PLL Block Diagram
27.6.1 Divider and Phase Lock Loop Programming
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the
corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus
the corresponding PLL input clock is set to 0.
The PLL (PLLA) allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that depends
on the respective source signal frequency and on the parameters DIV (DIVA) and MUL (MULA). The factor applied
to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0, the PLL is disabled and its power
consumption is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK (LOCKA) bit in PMC_SR is
automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT) in CKGR_PLLR (CKGR_PLLAR)
are loaded in the PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it reaches 0.
Divider
DIVA
PLLA
MULA
PLLACOUNT
LOCKA
OUTA
SLCK
MAINCK PLLACK
PLLA
Counter