Datasheet
51
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
10.4.3 Core registers
The processor core registers are:
Table 10-2. Core register set summary
Name Type
(1)
1. Describes access type during program execution in thread mode and Handler mode. Debug access can differ.
Required privilege
(2)
2. An entry of Either means privileged and unprivileged software can access the register.
Reset value Description
R0-R12 RW Either Unknown “General-purpose registers” on page 52
MSP RW Privileged See description “Stack Pointer” on page 52
PSP RW Either Unknown “Stack Pointer” on page 52
LR RW Either 0xFFFFFFFF “Link Register” on page 52
PC RW Either See description “Program Counter” on page 52
PSR RW Privileged
0x01000000
“Program Status Register” on page 52
ASPR RW Either 0x00000000 “Application Program Status Register” on page 54
IPSR RO Privileged 0x00000000 “Interrupt Program Status Register” on page 54
EPSR RO Privileged 0x01000000 “Execution Program Status Register” on page 55
PRIMASK RW Privileged 0x00000000 “Priority Mask Register” on page 57
FAULTMASK RW Privileged 0x00000000 “Fault Mask Register” on page 58
BASEPRI RW Privileged 0x00000000 “Base Priority Mask Register” on page 59
CONTROL RW Privileged 0x00000000 “CONTROL register” on page 60