Datasheet

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SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
10.3.2 Integrated configurable debug
The Cortex-M3 processor implements a complete hardware debug solution. This provides high system visibility of
the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is
ideal for microcontrollers and other small package devices.
For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints
and a profiling unit. To enable simple and cost-effective profiling of the system events these generate, a Serial
Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information
through a single pin.
10.3.3 Cortex-M3 processor features and benefits summary
tight integration of system peripherals reduces area and development costs
Thumb instruction set combines high code density with 32-bit performance
code-patch ability for ROM system updates
power control optimization of system components
integrated sleep modes for low power consumption
fast code execution permits slower processor clock or increases sleep mode time
hardware division and fast multiplier
deterministic, high-performance interrupt handling for time-critical applications
memory protection unit (MPU) for safety-critical applications
extensive debug and trace capabilities:
Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing.
10.3.4 Cortex-M3 core peripherals
These are:
10.3.4.1 Nested Vectored Interrupt Controller
The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that supports low latency
interrupt processing.
10.3.4.2 System control block
The System control block (SCB) is the programmers model interface to the processor. It provides system
implementation information and system control, including configuration, control, and reporting of system
exceptions.
10.3.4.3 System timer
The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating System (RTOS) tick
timer or as a simple counter.
10.3.4.4 Memory protection unit
The Memory protection unit (MPU) improves system reliability by defining the memory attributes for different
memory regions. It provides up to eight different regions, and an optional predefined background region.