Datasheet

47
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
10. ARM Cortex
®
M3 Processor
10.1 About this section
This section provides the information required for application and system-level software development. It does not
provide information on debug components, features, or operation.
This material is for microcontroller software and hardware engineers, including those who have no experience of
ARM products.
Note: The information in this section is reproduced from source material provided to Atmel by ARM Ltd. in terms of
Atmel’s license for the ARM Cortex
™
-M3 processor core. This information is copyright ARM Ltd., 2008 - 2009.
10.2 Embedded Characteristics
 Version 2.0
 Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit.
 Harvard processor architecture enabling simultaneous instruction fetch with data load/store.
 Three-stage pipeline.
 Single cycle 32-bit multiply.
 Hardware divide.
 Thumb and Debug states.
 Handler and Thread modes.
 Low latency ISR entry and exit.
 SysTick Timer
 24-bit down counter
 Self-reload capability
 Flexible system timer
 Nested Vectored Interrupt Controller
 Thirty maskable interrupts
 Sixteen priority levels
 Dynamic reprioritization of interrupts
 Priority grouping
selection of preempting interrupt levels and non preempting interrupt levels.
 Support for tail-chaining and late arrival of interrupts.
back-to-back interrupt processing without the overhead of state saving and restoration between
interrupts.
 Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no
instruction overhead.
10.3 About the Cortex-M3 processor and core peripherals
 The Cortex-M3 processor is a high performance 32-bit processor designed for the microcontroller market. It
offers significant benefits to developers, including:
 outstanding processing performance combined with fast interrupt handling
 enhanced system debug with extensive breakpoint and trace capabilities
 efficient processor core, system and memories
 ultra-low power consumption with integrated sleep modes
 platform security, with integrated memory protection unit (MPU).