Datasheet

457
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
25.16.3.1 NAND Flash Controller Timing Engine
When the NFC Command register is written, the NFC issues a NAND Flash Command and optionally performs a
data transfer between the NFC SRAM and the NAND Flash device. The NAND Flash Controller Timing Engine
guarantees valid NAND Flash timings, depending on the set of parameters decoded from the address bus. These
timings are defined in the SMC_TIMINGS register.
For information of the timing used depending on the command, see Figure 25-36:
Figure 25-36. NAND Flash Controller Timing Engine
See ”NFC Address Command” register description and ”SMC Timings Register”.
NFCEN=1 NFCWR =1 TADL =1
NFCEN=1 NFCWR=0 TWB != 0
NFCEN=0 VCMD2=1 TCLR != 0
!NFCEN=1 VCMD2=0 ACYCLE!=0 NFCWR=1 TADL != 0
!NFCEN=1 VCMD2=0 ACYCLE!=0 NFCWR=0 TAR != 0
!NFCEN=1 VCMD2=0 ACYCLE!=0 TCLR != 0
Wait TADL
Wait TADL
Wait TAR
Wait TWB
Wait TCLR
Wait TCLR
Timing Check Engine