Datasheet

433
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
25.10.4.2 Write is Controlled by NCS (WRITE_MODE = 0)
Figure 25-12 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus
during the pulse and hold steps of the NCS signal. The internal data buffers are turned out after the
NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE.
Figure 25-12. WRITE_MODE = 0. The write operation is controlled by NCS
25.10.5 Coding Timing Parameters
All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according
to their type.
 The SMC_SETUP register groups the definition of all setup parameters: NRD_SETUP, NCS_RD_SETUP,
NWE_SETUP, NCS_WR_SETUP
 The SMC_PULSE register groups the definition of all pulse parameters: NRD_PULSE, NCS_RD_PULSE,
NWE_PULSE, NCS_WR_PULSE
 The SMC_CYCLE register groups the definition of all cycle parameters: NRD_CYCLE, NWE_CYCLE
Table 25-6 shows how the timing parameters are coded and their permitted range.
MCK
D[15:0]
NCS
NWE,
NWR0, NWR1
A
[23:2]
NBS0, NBS1,
A0, A1
Table 25-6. Coding and Range of Timing Parameters
Coded Value Number of Bits Effective Value
Permitted Range
Coded Value Effective Value
setup [5:0] 6 128 x setup[5] + setup[4:0] 0 ≤ ≤ 31 128 ≤ ≤ 128+31
pulse [6:0] 7 256 x pulse[6] + pulse[5:0] 0 ≤ ≤ 63 256 ≤ ≤ 256+63
cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0] 0 ≤ ≤ 127
256 ≤ ≤ 256+127
512 ≤ ≤ 512+127
768 ≤ ≤ 768+127