Datasheet

423
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
25.7 Product Dependencies
25.7.1 I/O Lines
The pins used for interfacing the Static Memory Controller are multiplexed with the PIO lines. The programmer
must first program the PIO controller to assign the Static Memory Controller pins to their peripheral function. If I/O
Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller.
25.7.2 Power Management
The SMC is clocked through the Power Management Controller (PMC), thus the programmer must first configure
the PMC to enable the SMC clock.
25.7.3 Interrupt
The SMC has an interrupt line connected to the Nested Vector Interrupt Controller (NVIC). Handling the SMC
interrupt requires programming the NVIC before configuring the SMC.
25.8 External Memory Mapping
Note: 1. See Section 25.16.2 ”NFC Control Registers”, i.e., CMD_ADDR description.
The SMC provides up to 24 address lines, A[23:0]. This allows each chip select line to address up to 16 Mbytes of
memory.
If the physical memory device connected on one chip select is smaller than 16 Mbytes, it wraps around and
appears to be repeated within this space. The SMC correctly handles any valid access to the memory device
within the page (see Figure 25-3).
A[23:0] is only significant for 8-bit memory, A[23:1] is used for 16-bit memory.
Table 25-3. Peripheral IDs
Instance ID
SMC 9
Table 25-4. External Memory Mapping
Address Use Access
0x60000000-0x60FFFFFF Chip Select 0 (16 MB) Read-write
0x61000000-0x61FFFFFF Chip Select 1 Read-write
0x62000000-0x62FFFFFF Chip Select 2 Read-write
0x63000000-0x63FFFFFF Chip Select 3 Read-write
0x64000000-0x64FFFFFF Chip Select 4 Read-write
0x65000000-0x65FFFFFF Chip Select 5 Read-write
0x66000000-0x66FFFFFF Chip Select 6 Read-write
0x67000000-0x67FFFFFF Chip Select 7 Read-write
0x68000000-0x6FFFFFFF NFC Command Registers
(1)
Read-write