Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
420
25.2 Embedded Characteristics
 16-Mbyte Address Space per Chip Select
 8- or 16-bit Data Bus
 Word, Halfword, Byte Transfers
 Byte Write or Byte Select Lines
 Programmable Setup, Pulse and Hold Time for Read Signals per Chip Select
 Programmable Setup, Pulse and Hold Time for Write Signals per Chip Select
 Programmable Data Float Time per Chip Select
 External Data Bus Scrambling/Unscrambling Function
 External Wait Request
 Automatic Switch to Slow Clock Mode
 NAND Flash Controller Supporting NAND Flash with Multiplexed Data/Address Buses
 Supports SLC NAND Flash Technology
 Hardware Configurable Number of Chip Selects from 1 to 8
 Programmable Timing on a per Chip Select Basis
 AHB Slave Interface
 Atmel APB Configuration Interface
 Programmable Flash Data Width 8 Bits or 16 Bits
 Supports Hardware Error Correcting Code (ECC), 1-bit Error Correction, 2-bit Error Detection
 Detection and Correction by Software
 Supports NAND Flash and SmartMedia
™
Devices with 8- or 16-bit Data Path
 Supports NAND Flash/SmartMedia with Page Sizes of 528, 1056, 2112 and 4224 Bytes, Specified by
Software
 Supports 1-bit Correction for a Page of 512, 1024, 2048 and 4096 Bytes with 8- or 16-bit Data Path
 Supports 1-bit Correction per 512 Bytes of Data for a Page Size of 512, 2048 and 4096 Bytes with 8-bit Data
Path
 Supports 1-bit Correction per 256 Bytes of Data for a Page Size of 512, 2048 and 4096 Bytes with 8-bit Data
Path