Datasheet

409
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
• CAS: CAS Latency
Reset value is two cycles.
In the SDRAMC, only a CAS latency of one, two and three cycles are managed.
Values which are not listed in the table must be considered as “reserved”.
• DBW: Data Bus Width
Reset value is 16 bits
This field defines the Data Bus Width, which is 16 bits. It must be set to 1.
• TWR: Write Recovery Delay
Reset value is two cycles.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15.
• TRC_TRFC: Row Cycle Delay and Row Refresh Cycle
Reset value is seven cycles.
This field defines two timings:
the delay (t
RFC
) between two Refresh commands,
the delay (t
RFC
) between Refresh command and an Activate command
and the delay (t
RC
) between two Active commands in number of cycles.
The number of cycles is between 0 and 15. The end user will have to program max {t
RC
, t
RFC
}.
• TRP: Row Precharge Delay
Reset value is three cycles.
This field defines the delay between a Precharge Command and another Command in number of cycles. Number of cycles
is between 0 and 15.
• TRCD: Row to Column Delay
Reset value is two cycles.
This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of
cycles is between 0 and 15.
• TRAS: Active to Precharge Delay
Reset value is five cycles.
This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of
cycles is between 0 and 15.
• TXSR: Exit Self Refresh to Active Delay
Reset value is eight cycles.
This field defines the delay between SCKE set high and an Activate Command in number of cycles. Number of cycles is
between 0 and 15.
Value Name Description
01 LATENCY1 1 cycle CAS latency
10 LATENCY2 2 cycle CAS latency
11 LATENCY3 3 cycle CAS latency