Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
408
24.7.3 SDRAMC Configuration Register
Name: SDRAMC_CR
Address: 0x400E0208
Access: Read-write
Reset: 0x852372C0
Warning: bit 7 (DBW) must always be set to 1 when programming the SDRAMC_CR register.
• NC: Number of Column Bits
Reset value is 8 column bits.
• NR: Number of Row Bits
Reset value is 11 row bits.
Values which are not listed in the table must be considered as “reserved”.
• NB: Number of Banks
Reset value is two banks.
31 30 29 28 27 26 25 24
TXSR TRAS
23 22 21 20 19 18 17 16
TRCD TRP
15 14 13 12 11 10 9 8
TRC_TRFC TWR
76543210
DBW CAS NB NR NC
Value Name Description
00 COL8 8 column bits
01 COL9 9 column bits
10 COL10 10 column bits
11 COL11 11 column bits
Value Name Description
00 ROW11 11 row bits
01 ROW12 12 row bits
10 ROW13 13 row bits
Value Name Description
0 BANK2 2 banks
1 BANK4 4 banks