Datasheet

403
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
24.6.5.2Low-power Mode
This mode is selected by programming the LPCB field to 2 in the SDRAMC Low Power Register. Power
consumption is greater than in self-refresh mode. All the input and output buffers of the SDRAM device are
deactivated except SDCKE, which remains low. In contrast to self-refresh mode, the SDRAM device cannot
remain in low-power mode longer than the refresh period (64 ms for a whole device refresh operation). As no auto-
refresh operations are performed by the SDRAM itself, the SDRAM Controller carries out the refresh operation.
The exit procedure is faster than in self-refresh mode.
This is described in Figure 24-7.
Figure 24-7. Low-power Mode Behavior
SDCK
SDCS
RAS
CAS
SDRAMC_A[12:0]
DATA
(input)
T
RCD
= 3
Dna Dnb Dnc Dnd
Dne
Dnf
Row n col a col b col c col d col e col f
CAS = 2
SDCKE
Low Power Mode