Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
402
24.6.5.1 Self-refresh Mode
This mode is selected by programming the LPCB field to 1 in the SDRAMC Low Power Register. In self-refresh
mode, the SDRAM device retains data without external clocking and provides its own internal clocking, thus
performing its own auto-refresh cycles. All the inputs to the SDRAM device become “don’t care” except SDCKE,
which remains low. As soon as the SDRAM device is selected, the SDRAM Controller provides a sequence of
commands and exits self-refresh mode.
Some low-power SDRAMs (e.g., mobile SDRAM) can refresh only one quarter or a half quarter or all banks of the
SDRAM array. This feature reduces the self-refresh current. To configure this feature, Temperature Compensated
Self Refresh (TCSR), Partial Array Self Refresh (PASR) and Drive Strength (DS) parameters must be set in the
Low Power Register and transmitted to the low-power SDRAM during initialization.
After initialization, as soon as PASR/DS/TCSR fields are modified and self-refresh mode is activated, the
Extended Mode Register is accessed automatically and PASR/DS/TCSR bits are updated before entry into self-
refresh mode. This feature is not supported when SDRAMC shares an external bus with another controller.
The SDRAM device must remain in self-refresh mode for a minimum period of t
RAS
and may remain in self-refresh
mode for an indefinite period. This is described in Figure 24-6.
Figure 24-6. Self-refresh Mode Behavior
SDCK
SDCS
RAS
CAS
S
DRAMC_A[12:0]
Self Refresh Mode
SDWE
Row
T
XSR
= 3
SDCKE
Write
SDRAMC_SRR
SRCB = 1
Access Request
to the SDRAM Controller