Datasheet

397
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
24.5.4 Power Management
The SDRAM Controller may be clocked through the Power Management Controller (PMC), thus the programmer
must first configure the PMC to enable the SDRAM Controller clock. The SDRAM Controller Clock (not the SDCK
pin) is managed by the Static Memory Controller Clock.
The SDRAM Clock on SDCK pin will be output as soon as the first access to the SDRAM is done during the
initialization phase.
If one needs to stop the SDRAM clock signal, the Low Power Mode Register (SDRAMC_LPR) must be
programmed with the sefl-refresh command.