Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
392
24. AHB SDRAM Controller (SDRAMC)
24.1 Description
The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to an
external 16-bit DRAM device. The page size supports ranges from 2048 to 8192 and the number of columns from
256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses.
The SDRAM Controller supports a read or write burst length of one location. It keeps track of the active row in each
bank, thus maximizing SDRAM performance, e.g., the application may be placed in one bank and data in the other
banks. So as to optimize performance, it is advisable to avoid accessing different rows in the same bank.
The SDRAM controller supports a CAS latency of 1, 2 or 3 and optimizes the read access depending on the
frequency.
The different modes available - self-refresh, power-down and deep power-down modes - minimize power
consumption on the SDRAM device.
24.2 Embedded Characteristics
 Numerous Configurations Supported
 2K, 4K, 8K Row Address Memory Parts
 SDRAM with Two or Four Internal Banks
 SDRAM with 16-bit Data Path
 Programming Facilities
 Word, Half-word, Byte Access
 Automatic Page Break When Memory Boundary Has Been Reached
 Multibank Ping-pong Access
 Timing Parameters Specified by Software
 Automatic Refresh Operation, Refresh Rate is Programmable
 Automatic Update of DS, TCR and PASR Parameters (Mobile SDRAM Devices)
 Energy-saving Capabilities
 Self-refresh, Power-down and Deep Power Modes Supported
 Supports Mobile SDRAM Devices
 Error Detection
 Refresh Error Interrupt
 SDRAM Power-up Initialization by Software
 CAS Latency of 1, 2, 3 Supported
 Auto Precharge Command Not Used