Datasheet

39
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
9.2 APB/AHB Bridge
The SAM3X/A series product embeds two separate APB/AHB bridges:
 a low speed bridge
 a high speed bridge
This architecture enables a concurrent access on both bridges.
SPI, SSC and HSMCI peripherals are on the high-speed bridge connected to DMAC with the internal FIFO for
Channel buffering.
UART, ADC, TWI0–1, USART0–3, PWM, DAC and CAN peripherals are on the low-speed bridge and have
dedicated channels for the Peripheral DMA Channels (PDC). Note that USART0–1 can be used with the DMA as
well.
The peripherals on the high speed bridge are clocked by MCK. On the low-speed bridge, CAN controllers can be
clocked at MCK divided by 2 or 4. Refer to Section 27. “Clock Generator”.
9.3 Peripheral Signal Multiplexing on I/O Lines
The SAM3X/A series product features up to six PIO controllers (PIOA, PIOB, PIOC, PIOD, PIOE, and PIOF) which
multiplex the I/O lines of the peripheral set:
 3 PIO controllers on SAM3A and 100-pin SAM3X
 4 PIO controllers on 144-pin SAM3X
 6 PIO controllers on 217-pin SAM3X8H
(1)
Each PIO controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B.
The multiplexing tables in the following pages define how the I/O lines of the peripherals A and B are multiplexed
on the PIO controllers.
Note that some output-only peripheral functions might be duplicated within the tables.
Note: 1. This device is not commercially available. Mounted only on the SAM3X-EK evaluation kit.
30 TC3 X X Timer Counter Channel 3
31 TC4 X X Timer Counter Channel 4
32 TC5 X X Timer Counter Channel 5
33 TC6 X X Timer Counter Channel 6
34 TC7 X X Timer Counter Channel 7
35 TC8 X X Timer Counter Channel 8
36 PWM X X Pulse Width Modulation Controller
37 ADC X X ADC Controller
38 DACC X X DAC Controller
39 DMAC X X DMA Controller
40 UOTGHS X X USB OTG High Speed
41 TRNG X X True Random Number Generator
42 EMAC X X Ethernet MAC
43 CAN0 X X CAN Controller 0
44 CAN1 X X CAN Controller 1
Table 9-1. Peripheral Identifiers (Continued)
Instance
ID Instance Name
NVIC
Interrupt
PMC
Clock Control Instance Description