Datasheet

387
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
23.7 Functional Description
The external memory bus transfers data between the internal AHB Bus (handled by the memory controllers) and
the external memories or peripheral devices. It controls the waveforms and the parameters of the external
address, data and control buses and is composed of the following elements:
 Static Memory Controller (SMC)
 NAND Flash Controller (NFC)
 SDRAM Controller (SDRAMC)
 ECC Controller (ECC)
23.7.1 Bus Multiplexing
The external memory bus offers a complete set of control signals that share the 16-bit data lines, the address lines
of up to 24 bits and the control signals through a multiplex logic operating in function of the memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines
at a stable state while no external access is being performed. Multiplexing is also designed to respect the data float
times defined in the Memory Controllers. Furthermore, refresh cycles of the SDRAM are executed independently
by the SDRAM Controller without delaying the other external Memory Controller accesses.
23.7.2 Static Memory Controller
For information on the Static Memory Controller, refer to Section 25. “Static Memory Controller (SMC)”.
23.7.3 NAND Flash Controller
For information on the NAND Flash Controller, refer to Section 25. “Static Memory Controller (SMC)”.
23.7.4 SDRAM Controller
For information on the SDRAM Controller, refer to Section 24. “AHB SDRAM Controller (SDRAMC)”.
23.7.5 ECC Controller
For information on the ECC Controller, refer to Section 25. “Static Memory Controller (SMC)”.