Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
384
23.4 I/O Lines Description
The connection of some signals through the Mux logic is not direct and depends on the Memory Controller in use
at the moment.
Table 23-1. I/O Lines Description
Name Function Type Active Level
External Memory Bus
D[15:0] Data Bus I/O
A[23:0] Address Bus Output
Static Memory Controller (SMC)
NCS[7:0] Chip Select Lines Output Low
NWR0/NWE Write Signals Output Low
NRD Read Signal Output Low
NWR1/NBS1 Write Enable/Upper Byte Select Output Low
A0/NBS0 Lower Byte Select Output Low
NWAIT External Wait Signal Input Low
NAND Flash Controller (NFC)
NCS[7:0] Chip Select Lines Output Low
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
NANDCLE NAND Flash Command Line Enable Output Low
NANDALE NAND Flash Address Line Enable Output Low
NANDRDY NAND Flash Ready/Busy Input Low
SDR-SDRAM Controller
SDCK SDRAM Clock Output
SDCKE SDRAM Clock Enable Output High
SDCS SDRAM Controller Chip Select Line Output Low
BA[1:0] Bank Select Output
SDWE SDRAM Write Enable Output Low
RAS - CAS Row and Column Signal Output Low
NBS[1:0] Byte Mask Signals Output Low
SDA10 SDRAM Address 10 Line Output