Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
36
 Multiple device adaptability
 Control signals programmable setup, pulse and hold time for each Memory Bank
 Multiple Wait State Management
 Programmable Wait State Generation
 External Wait Request
 Programmable Data Float Time
 Slow Clock mode supported
7.3.3 NAND Flash Controller
 Handles automatic Read/write transfer through 4224 bytes SRAM buffer
 DMA support
 Supports SLC NAND Flash technology
 Programmable timing on a per chip select basis
 Programmable Flash Data width 8-bit or 16-bit
7.3.4 NAND Flash Error Corrected Code Controller
 Integrated in the NAND Flash Controller
 Single bit error correction and 2-bit Random detection.
 Automatic Hamming Code Calculation while writing
 ECC value available in a register
 Automatic Hamming Code Calculation while reading
 Error Report, including error flag, correctable error flag and word address being detected erroneous
 Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte pages
7.3.5 SDR-SDRAM Controller (217-pin SAM3X8H
(l)
only)
 Numerous configurations supported
 2K, 4K, 8K Row Address Memory Parts
 SDRAM with two or four Internal Banks
 SDRAM with 16-bit Data Path
 Programming facilities
 Word, half-word, byte access
 Automatic page break when Memory Boundary has been reached
 Multibank Ping-pong Access
 Timing parameters specified by software
 Automatic refresh operation, refresh rate is programmable
 Energy-saving capabilities
 Self-refresh, and Low-power Modes supported
 Error detection
 Refresh Error Interrupt
 SDRAM Power-up Initialization by software
 Latency is set to two clocks (CAS Latency of 1, 3 Not Supported)
 Auto Precharge Command not used
 Mobile SDRAM supported (except for low-power extended mode and deep power-down mode)
Note: 1. This device is not commercially available. Mounted only on the SAM3X-EK evaluation kit.