Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
356
22.5 DMAC Software Requirements
 There must not be any write operation to Channel registers in an active channel after the channel enable is
made HIGH. If any channel parameters must be reprogrammed, this can only be done after disabling the
DMAC channel.
 When the destination peripheral has been defined as the flow controller, source single transfer requests are
not serviced until the destination peripheral has asserted its Last Transfer Flag.
 When the source peripheral has been defined as the flow controller, destination single transfer requests are
not serviced until the source peripheral has asserted its Last Transfer Flag.
 When the destination peripheral has been defined as the flow controller, if the destination width is smaller
than the source width, then a data loss may occur, and the loss is equal to the Source Single Transfer size in
bytes- destination Single Transfer size in bytes.
 When a Memory to Peripheral transfer occurs, if the destination peripheral has been defined as the flow
controller, then a prefetch operation is performed. It means that data is extracted from the memory before
any request from the peripheral is generated.
 You must program the DMAC_SADDRx and DMAC_DADDRx channel registers with a byte, half-word and
word aligned address depending on the source width and destination width.
 After the software disables a channel by writing into the channel disable register, it must re-enable the
channel only after it has polled a 0 in the corresponding channel enable status register. This is because the
current AHB Burst must terminate properly.
 If you program the BTSIZE field in the DMAC_CTRLA as zero, and the DMAC has been defined as the flow
controller, then the channel is automatically disabled.
 When hardware handshaking interface protocol is fully implemented, a peripheral is expected to deassert
any sreq or breq signals on receiving the ack signal irrespective of the request the ack was asserted in
response to.
 Multiple Transfers involving the same peripheral must not be programmed and enabled on different
channels, unless this peripheral integrates several hardware handshaking interfaces.
 When a Peripheral has been defined as the flow controller, the targeted DMAC Channel must be enabled
before the Peripheral. If you do not ensure this and the First DMAC request is also the last transfer, the
DMAC Channel might miss a Last Transfer Flag.