Datasheet

SAM3X / SAM3A [DATASHEET]

Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15

350

Figure 22-7. DMAC Transfer Flow for Source and Destination Linked List Address

 i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow

control device by programming the FC of the DMAC_CTRLBx register.

 i. Designate the handshaking interface type (hardware or software) for the source and destination

peripherals. This is not required for memory. This step requires programming the

SRC_H2SEL/DST_h2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking

interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the

software handshaking interface to handle source/destination requests.

Channel enabled by

software

LLI Fetch

Hardware reprograms

SADDRx, DADDRx, CTRLA/Bx, DSCRx

DMAC buffer transfer

Writeback of DMAC_CTRLAx

Is DMAC in

Row 1 of

DMAC State Machine Table?

Channel disabled by

hardware

Chained Buffer Transfer Completed

Interrupt generated here

DMAC Chained Buffer Transfer

Completed Interrupt generated here

yes