Datasheet

35
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
7.2.3.10 GPNVM Bits
The SAM3X/A series features three GPNVM bits that can be cleared or set respectively through the “Clear
GPNVM Bit” and “Set GPNVM Bit” commands of the EEFC0 User Interface.
There is no GPNVM bit on Flash 1.
The GPNVM0 is the security bit.
The GPNVM1 is used to select the boot mode (boot always at 0x00) on ROM or Flash.
The GPNVM2 is used only to swap the Flash 0 and Flash 1. If GPNVM2 is ENABLE, the Flash 1 is mapped at
address 0x0008_0000 (Flash 1 and Flash 0 are continuous). If GPNVM2 is DISABLE, the Flash 0 is mapped at
address 0x0008_0000 (Flash 0 and Flash 1 are continuous).
7.2.4 Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be
changed via GPNVM.
A general-purpose NVM (GPNVM1) bit is used to boot either on the ROM (default) or from the Flash.
Setting GPNVM bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM. Asserting ERASE
clears GPNVM bit 1 and thus selects the boot from the ROM by default.
GPNVM2 enables to select if Flash 0 or Flash 1 is used for the boot.
Setting GPNVM bit 2 selects the boot from Flash 1, clearing it selects the boot from Flash 0.
7.3 External Memories
The 144-pin SAM3X and 217-pin SAM3X8H
(1)
feature one External Memory Bus to offer interface to a wide range
of external memories and to any parallel peripheral.
Note: 1. This device is not commercially available. Mounted only on the SAM3X-EK evaluation kit.
7.3.1 External Memory Bus
 Integrates Four External Memory Controllers:
 Static Memory Controller
 NAND Flash Controller
 SLC NAND Flash ECC Controller
 Single Data Rate Synchronous Dynamic Random Access Memory (SDR-SDRAM)
 Up to 24-bit Address Bus (up to 16 Mbytes linear per chip select)
 Up to 8 chip selects, Configurable Assignment
7.3.2 Static Memory Controller
 8- or 16-bit Data Bus
 Multiple Access Modes supported
 Byte Write or Byte Select Lines
 Asynchronous read in Page Mode supported (4- up to 32-byte page size)
Table 7-5. General Purpose Non-volatile Memory Bits
GPNVM Bit[#] Function
0 Security bit
1 Boot mode selection
2 Flash selection (Flash 0 or Flash 1)